X9C503SIT1 Intersil, X9C503SIT1 Datasheet - Page 5

• Manufacturer Part Number: X9C503SIT1
• Description: IC XDCP 100-TAP 50K EE 8-SOIC
• Manufacturer: Intersil
• Series: XDCP™r

Specifications of X9C503SIT1

• Taps: 100
• Resistance (ohms): 50K
• Number Of Circuits: 1
• Temperature Coefficient: 300 ppm/°C Typical
• Memory Type: Non-Volatile
• Interface: Up/Down (3-Wire)
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• Resistance In Ohms: 50K
• Number Of Elements: 1
• # Of Taps: 100
• Resistance (max): 50KOhm
• Power Supply Requirement: Single
• Interface Type: Serial (3-Wire)
• Single Supply Voltage (typ): 5V
• Dual Supply Voltage (typ): Not RequiredV
• Single Supply Voltage (min): 4.5V
• Single Supply Voltage (max): 5.5V
• Dual Supply Voltage (min): Not RequiredV
• Dual Supply Voltage (max): Not RequiredV
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 8
• Package Type: SOIC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Electrical Specifications
NOTES:
Endurance and Data Retention
AC Conditions of Test
Medium Endurance
Data Retention
Input Pulse Levels
Input Rise and Fall Times
Input Reference Levels
AC OPERATION CHARACTERISTICS
3. Absolute linearity is utilized to determine actual wiper voltage vs expected voltage = [V
4. Relative linearity is a measure of the error in step size between taps = V
5. 1 MI = Minimum Increment = R
6. Typical values are for T
7. This parameter is not 100% tested.
Test Circuit #1
SYMBOL
V
S
t
t
PARAMETER
t
t
IW
t
t
R
CPH
CPH
CYC
CYC
t
t
t
t
t
t
t
PU
Cl
lD
DI
lH
lC
, t
lL
(5)
F
CS to INC Setup
INC HIGH to U/D Change
U/D to INC Setup
INC LOW Period
INC HIGH Period
INC Inactive to CS Inactive
CS Deselect Time (STORE)
CS Deselect Time (NO STORE)
INC to V
INC Cycle Time
INC Input Rise and Fall Time
Power-up to Wiper Stable (Note 7)
V
CC
Power-up Rate (Note 7)
V
V
W/RW
A
R
L
/R
= +25°C and nominal supply voltage.
/R
L
H
100,000
Change
V
MIN
5
PARAMETER
100
w
TOT
Over recommended operating conditions unless otherwise stated. (Continued)
/R
TEST POINT
W
/99.
Data changes per bit
per register
years
X9C102, X9C103, X9C104, X9C503
0V to 3V
10ns
1.5V
UNIT
Test Circuit #2
V
V
H
L
/R
/R
TEST CONDITIONS
L
H
V
W
W(n + 1)
TEST POINT
/R
Power-up and Down Requirements
At all times, voltages on the potentiometer pins must be less
than ±V
memory is not in effect until the V
value. The V
w
FORCE
CURRENT
- [V
W(n)(actual)
CC
W(n) + MI
. The recall of the wiper position from non-volatile
CC
- V
] = +0.2 MI.
ramp rate specification is always in effect.
W(n)(expected )
Circuit #3 SPICE Macro Model
MIN
100
100
100
2.9
0.2
20
R
1
1
1
2
L
] = ±1 MI Maximum.
(Note 6)
LIMITS
TYP
10pF
100
500
C
L
CC
R
TOTAL
R
supply reaches its final
W
25pF
C
MAX
500
50
W
10pF
C
July 20, 2009
UNIT
V/ms
L
ms
ns
ns
µs
µs
µs
µs
ns
µs
µs
µs
µs
FN8222.3
R
H