X9408WV24I-2.7T2 Intersil, X9408WV24I-2.7T2 Datasheet - Page 4
![IC XDCP QUAD 64-TAP 10K 24-TSSOP](/photos/6/65/66570/20-24-tssop_sml.jpg)
X9408WV24I-2.7T2
Manufacturer Part Number
X9408WV24I-2.7T2
Description
IC XDCP QUAD 64-TAP 10K 24-TSSOP
Manufacturer
Intersil
Series
XDCP™r
Datasheet
1.X9408WS24I.pdf
(20 pages)
Specifications of X9408WV24I-2.7T2
Taps
64
Resistance (ohms)
10K
Number Of Circuits
4
Temperature Coefficient
300 ppm/°C Typical
Memory Type
Non-Volatile
Interface
I²C, 2-Wire Serial
Voltage - Supply
2.7 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
24-TSSOP
Resistance In Ohms
10K
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Principals of Operation
The X9408 is a highly integrated microcircuit incorporating
four resistor arrays and their associated registers and
counters and the serial interface logic providing direct
communication between the host and the XDCP
potentiometers.
Serial Interface
The X9408 supports a bidirectional bus oriented protocol.
The protocol defines any device that sends data onto the
bus as a transmitter and the receiving device as the receiver.
The device controlling the transfer is a master and the
device being controlled is the slave. The master will always
initiate data transfers and provide the clock for both transmit
and receive operations. Therefore, the X9408 will be
considered a slave device in all applications.
Clock and Data Conventions
Data states on the SDA line can change only during SCL
LOW periods (t
are reserved for indicating start and stop conditions.
Start Condition
All commands to the X9408 are preceded by the start
condition, which is a HIGH to LOW transition of SDA while
SCL is HIGH (t
SDA and SCL lines for the start condition and will not
respond to any command until this condition is met.
Stop Condition
All communications must be terminated by a stop condition,
which is a LOW to HIGH transition of SDA while SCL is
HIGH.
Acknowledge
Acknowledge is a software convention used to provide a
positive handshake between the master and slave devices
on the bus to indicate the successful receipt of data. The
transmitting device, either the master or the slave, will
release the SDA bus after transmitting eight bits. The master
generates a ninth clock cycle and during this period the
receiver pulls the SDA line LOW to acknowledge that it
successfully received the eight bits of data.
The X9408 will respond with an acknowledge after
recognition of a start condition and its slave address and
once again after successful receipt of the command byte. If
the command is followed by a data byte the X9408 will
respond with a final acknowledge.
Array Description
The X9408 is comprised of four resistor arrays. Each array
contains 63 discrete resistive segments that are connected
in series. The physical ends of each array are equivalent to
the fixed terminals of a mechanical potentiometer (R
R
L
inputs).
HIGH
LOW
). SDA state changes during SCL HIGH
). The X9408 continuously monitors the
4
H
and
X9408
At both ends of each array and between each resistor
segment is a CMOS switch connected to the wiper (R
output. Within each individual array only one switch may be
turned on at a time. These switches are controlled by the
Wiper Counter Register (WCR). The six bits of the WCR are
decoded to select, and enable, one of sixty-four switches.
The WCR may be written directly, or it can be changed by
transferring the contents of one of four associated Data
Registers into the WCR. These Data Registers and the WCR
can be read and written by the host system.
Device Addressing
Following a start condition the master must output the
address of the slave it is accessing. The most significant four
bits of the slave address are the device type identifier (refer
to Figure 1 below). For the X9408 this is fixed as 0101[B].
The next four bits of the slave address are the device
address. The physical device address is defined by the state
of the A
stream with the address input state; a successful compare of
all four address bits is required for the X9408 to respond with
an acknowledge. The A
by CMOS input signals or tied to V
Acknowledge Polling
The disabling of the inputs, during the internal Nonvolatile
write operation, can be used to take advantage of the typical
5ms EEPROM write cycle time. Once the stop condition is
issued to indicate the end of the nonvolatile write command
the X9408 initiates the internal write cycle. ACK polling can
be initiated immediately. This involves issuing the start
condition followed by the device slave address. If the X9408
is still busy with the write operation no ACK will be returned.
If the X9408 has completed the write operation an ACK will
be returned and the master can then proceed with the next
operation.
0
- A
0
3
DEVICE TYPE
IDENTIFIER
inputs. The X9408 compares the serial data
1
FIGURE 1. SLAVE ADDRESS
0
0
- A
1
3
inputs can be actively driven
A3
DEVICE ADDRESS
CC
A2
or V
SS
A1
.
January 15, 2009
A0
W
FN8191.4
)