X9258US24IZ-2.7 Intersil, X9258US24IZ-2.7 Datasheet - Page 9

• Manufacturer Part Number: X9258US24IZ-2.7
• Description: IC XDCP QUAD 256TP 50K 24-SOIC
• Manufacturer: Intersil
• Series: XDCP™r

Specifications of X9258US24IZ-2.7

• Taps: 256
• Resistance (ohms): 50K
• Number Of Circuits: 4
• Temperature Coefficient: 300 ppm/°C Typical
• Memory Type: Non-Volatile
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 24-SOIC (7.5mm Width)
• Resistance In Ohms: 50K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Wiper Counter Register, (8-bit), Volatile
One 8-bit Wiper Counter Register for each DCP (four 8-bit
registers in total.)
{D7~D0}: These bits specify the wiper position of the
respective DCP. The Wiper Counter Register is loaded on
power-up by the value in Data Register 0. The contents of
Read Wiper Counter Register (WCR)
Write Wiper Counter Register (WCR)
Read Data Register (DR)
Write Data Register (WR)
S
A
R
S
T
A
R
T
T
T
S
T
A
R
T
S
T
A
R
T
(MSB)
WP7
DEVICE TYPE
IDENTIFIER
0 1 0 1 A
V
0
IDENTIFIER
IDENTIFIER
0
DEVICE TYPE
0
DEVICE
IDENTIFIER
DEVICE
TYPE
TYPE
1
1
1
WP6
0
0
V
0
1 A3 A2 A1 A0
1 A3 A2 A1 A0
1 A3 A2 A1 A0
ADDRESSES
3
WP5
ADDRESSES S
ADDRESSES
DEVICE
ADDRESSES S
V
A
2
DEVICE
DEVICE
DEVICE
A
1
WP4
V
A
0
S
A
C
K
9
A
C
K
INSTRUCTION
WP3
1
A
C
K
S
A
C
K
V
INSTRUCTION
OPCODE
1
1
OPCODE
INSTRUCTION
1
INSTRUCTION
1
0
OPCODE
OPCODE
WP2
0
0
0
V
0
0
1
1
1 0 0 P1 P0
WP1
R1 R0 P1 P0
DR AND WCR
ADDRESSES
V
ADDRESSES S
1
0
R1 R0 P1 P0
WCR
0 0 P1 P0
ADDRESSES
DR AND WCR
ADDRESSES
(LSB)
WP0
V
WCR
X9258
A
C
K
S
A
C
K
WP7 WP6 WP5 WP4 WP3 WP2 WP1 WP0
WP7 WP6 WP5 WP4 WP3 WP2 WP1 WP0
S
A
C
K
A
C
K
S
the WCR can be loaded from any of the other Data Register
or directly. The contents of the WCR can be saved in a DR.
Instruction Format
NOTES:
WP7 WP6 WP5 WP4 WP3 WP2 WP1 WP0
2. “MACK”/”SACK”: stands for the acknowledge sent by the
3. “A3 ~ A0”: stands for the device addresses sent by the master.
4. “X”: indicates that it is a “0” for testing purpose but physically it is
5. “I”: stands for the increment operation, SDA held high during
6. “D”: stands for the decrement operation, SDA held low during
WP7 WP6 WP5 WP4 WP3 WP2 WP1 WP0
master/slave.
a “don’t care” condition.
active SCL phase (high).
active SCL phase (high).
(SENT BY SLAVE ON SDA)
(SENT BY MASTER ON SDA)
WIPER POSITION
(SENT BY MASTER ON SDA)
(SENT BY SLAVE ON SDA)
DATA BYTE
DATA BYTE
DATA BYTE
M
A
C
K
S
A
C
K
O
S
T
P
S
O
P
T
HIGH-VOLTAGE
WRITE CYCLE
M
A
C
K
S
A
C
K
April 14, 2011
S
O
P
T
O
S
T
P
FN8168.5