DS3908N+T&R Maxim Integrated Products, DS3908N+T&R Datasheet - Page 8

IC POT DUAL DIGITAL 14-TDFN

DS3908N+T&R

Manufacturer Part Number
DS3908N+T&R
Description
IC POT DUAL DIGITAL 14-TDFN
Manufacturer
Maxim Integrated Products
Datasheet

Specifications of DS3908N+T&R

Taps
64
Resistance (ohms)
100K
Number Of Circuits
2
Temperature Coefficient
50 ppm/°C Typical
Memory Type
Non-Volatile
Interface
I²C, 2-Wire Serial
Voltage - Supply
3 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
14-TDFN Exposed Pad
Resistance In Ohms
100K
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Dual, 64-Position Nonvolatile Digital
Potentiometer with Buffered Outputs
When writing to the DS3908, the potentiometer will
adjust to the new setting once it has acknowledged the
new data that is being written, and the EEPROM (used
to make the setting nonvolatile) will be written following
the stop condition at the end of the write command. To
change the setting without changing the EEPROM, ter-
minate the write with a repeated start condition before
the next stop condition occurs. Using a repeated start
Table 2. Programmable Amplifier Register
Table 3. Programmable Amplifier Gain Codes
Writes to this register are similar to writes to the poten-
tiometer register. A stop condition must follow the write
to ensure that the EEPROM is modified. A repeated
start condition before a stop condition following a write
operation will prevent the settings from being stored in
EEPROM. (See the I
more details.)
Default value = 11h.
*Reserved for future use, write to zeros.
X = Don’t care.
8
FBh
ADDRESS
_____________________________________________________________________
Gx
2
Gx
00X
01X
1XX
1
Gx
bit7
R*
0
2
C Communication section for
G1
AMPLIFIER GAIN (V/V)
2
PGA1
1
2
4
G1
1
REGISTER FORMAT (BINARY)
G1
0
condition prevents the 20ms (maximum) delay required
for the EEPROM write cycle to finish.
The gain of both DS3908 amplifiers is controlled by
writing to register address FBh. The most significant
nibble of the FBh address controls the PGA1 gain, and
the least significant nibble controls the PGA0 gain. The
format of each nibble is shown in the tables below:
The write-protect pin has an internal pullup resistor. To
adjust the potentiometers’ position, this pin must be
grounded. This pin can be left floating or connected to
V
can be read when the device is write protected.
CC
to write protect the EEPROM memory. All registers
R*
Programmable Amplifier Control
G0
2
PGA0
G0
Write Protection
1
G0
bit0
0

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