CAT5140ZI-00-GT3 ON Semiconductor, CAT5140ZI-00-GT3 Datasheet - Page 9

• Manufacturer Part Number: CAT5140ZI-00-GT3
• Description: IC POT DGTL 256TAP I2C/EEP 8MSOP
• Manufacturer: ON Semiconductor

Specifications of CAT5140ZI-00-GT3

• Taps: 256
• Resistance (ohms): 100K
• Number Of Circuits: 1
• Temperature Coefficient: 100 ppm/°C Typical
• Memory Type: Non-Volatile
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-MSOP
• Resistance In Ohms: 100K
• Number Of Pots: Single
• Taps Per Pot: 256
• Resistance: 100 KOhms
• Wiper Memory: Volatile
• Buffered Wiper: Buffered
• Digital Interface: I2C
• Operating Supply Voltage: 3.3 V
• Supply Current: 3 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.5 V
• Tolerance: 20 %
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Single write to either a volatile or non−volatile register. Note that Bit 7 of ACR determines which memory type is being written.
A single write to either a volatile or non−volatile register. At address 00h bit 7 of ACR determines which memory type is being written.
Multiple writes are possible only if the starting address is 08h and it should be stopped with the first nonvolatile data byte. If
a nonvolatile write does not end with a STOP procedure the register is not written.
(B) Read data procedure with designated address.
(C) Read data procedure without a designated address.
Table 15. SINGLE WRITE
Table 16. MULTIPLE WRITES
Table 17. READ DATA
Table 18. Read Data w/o Designated Address
10. Host transfers ACK signal
11. The (9) & (10) routines above are repeated if needed, and the read address is auto−incremented
12. Host transfers ACK ‘H’ to the device
13. Host transfers the stop condition
Start
1. Host transfers the start condition
2. Host transfers the device slave address with the write mode R/W bit (0)
3. ACK signal recognition from the device
4. Host transfers the read address
5. ACK signal recognition from the device
6. Host transfers the re−start condition
7. Host transfers the slave address with the read mode R/W bit (1).
8. ACK signal recognition from the device
9. The device transfers the read data from the designated address
(1)
1. Host transfers the start condition
2. Host transfers the device slave address with the read mode R/W bit =1
3. ACK signal recognition from the device. (Host then changes to receiver)
4. The device transfers data from the previous access address +1
5. Host transfers ACK signal
6. The (4) & (5) routines above are repeated if needed
7. Host transfers ACK ‘H’
8. Host transfers the stop condition
Start
Start
Start
(1)
(1)
(1)
Address
Slave
(2)
Address
Slave
Address
Address
Slave
Slave
R/W
0
(2)
(2)
(2)
ACK
(3)
0
R/W
0
R/W
R/W
0
1
Memory
Address
(4)
ACK
(3)
0
ACK
ACK
(3)
(3)
0
ACK
0
(5)
0
Memory
Address
Restart
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(4)
(6)
Address
Memory
Read
Data
(4)
(4)
Address
9
Slave
ACK
(5)
0
(7)
ACK
R/W
ACK
(5)
Write
1
(5)
0
Data
0
(6)
ACK
(8)
0
ACK
(7)
0
Write
Data
Read
Data
(6)
Read
Data
(6)
(9)
Write
Data
ACK
(10)
0
ACK
ACK
(8)
(7)
(7)
0
1
Read
Data
(11)
ACK
0
ACK
(12)
1
Stop
Stop
(9)
(8)
Stop
(9)
Stop
(13)