ISL6617CRZ Intersil, ISL6617CRZ Datasheet - Page 8

• Manufacturer Part Number: ISL6617CRZ
• Description: Phase Splitter, Commercial, 10LD 3X3 DFN
• Manufacturer: Intersil

Timing Diagram
Operation
Designed for high phase count and phase shedding
applications, the ISL6617 driverless phase doubler is
meant to double or quadruple (cascaded option using
two ISL6617s) the number of phases that Intersil’s
multi-phase controllers ISL63xx can support. Further, the
PWM line can be pulled high to disable the respective
phase and higher phase(s) when the enable pin
(EN_PH_SYNC) is pulled low. This simplifies the phase
shedding implementation for the controller that can
disable the respective and higher phase(s) by pulling the
respective PWM input high.
A rising transition on PWMIN initiates the turn-on of the
PWMA/B (see Figure 1). After a short propagation delay
[t
[t
on page 7.
A falling transition on PWMIN indicates the turn-off of
the PWMA/B. The PWMA/B begins to fall [t
propagation delay [t
current balance circuits.
When the PWMIN stays in the tri-state window for longer
than [t
cascaded 5V PWM input MOSFET driver or integrated
power stage can recognize tri-state.
EN_PH_SYNC Operation
The EN_PH_SYNC pin features multiple functions. It is
the enable input of the device and the input to select
various operational modes.
A. ENABLE OPERATION
PWMA/B
PWMIN
EN_PH_SYNC
PWMIN
PWMA/B
FIGURE 2. TYPICAL ENABLE OPERATION TIMING
PDH
R1
] are provided in the “Electrical Specifications” table
], the PWMA/B begins to rise. Typical rise times
TSSHD
10%
DIAGRAM
], both PWMA/B will pull to ~2V so that the
t
R1
t
PDH
90%
PDL
], which is modulated by the
8
t
PDL
t
F1
90%
F1
FIGURE 1. TIMING DIAGRAM
] after a
10%
2.5V
ISL6617
ISL6617
t
TSSHD
As shown in Figure 2, the ISL6617 disables the doubler
operation when the EN_PH_SYNC pin is pulled to
ground, while the PWMIN pin is pulled to VCC. With the
PWM line pulled high, some Intersil controllers such as
VR10, VR11, VR11.1 and VR12 family can disable the
respective and higher phase(s). When the
EN_PH_SYNC returns high, the phase doubler will pull
the PWM line into tri-state window, and then will be
enabled only at the leading edge of PWM input. Prior to
the first PWMin rising edge, both the PWMA and PWMB
output will remain in tri-state unless an overvoltage
fault is detected. This fault is defined as when a phase
is detected to have more than 60% of the maximum
I
load if the upper MOSFET experiences a short while the
doubler is enabled.
The EN_PH_SYNC pin should remain high if driving the
PWM line high is prohibited for the associated
controller. For proper system interface, please refer to
the device data sheets.
B. SYNCHRONOUS OPERATION
The ISL6617 can be set in interleaving mode or
synchronous mode by pulling the EN_PH_SYNC pin to the
respective level, shown in Table 1. A synchronous pulse
can be sent to the phase doubler during the load
application to improve the voltage droop and current
balance while still maintaining interleaving operation at DC
load conditions. However, excessive ringback can occur;
hence, the synchronous mode operation should be
carefully investigated. Figure 3 shows how to generate a
synchronous pulse when a transient load is applied. The
comparator should be a fast comparator with a minimum
delay.
OUT
COMP
FIGURE 3. TYPICAL SYNC PULSE GENERATOR
current. This provides additonal protection to the
t
PTS
15ns
20kΩ
2kΩ
10%
t
R2
t
TSSHD
49.9kΩ
1.0nF
90%
+
-
60%
VCC
0Ω
t
F2
t
PTS
1kΩ
DNP
February 4, 2010
SYNC
FN7564.0