SST39WF1601-70-4C-Y1QE Microchip Technology, SST39WF1601-70-4C-Y1QE Datasheet
SST39WF1601-70-4C-Y1QE
Specifications of SST39WF1601-70-4C-Y1QE
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SST39WF1601-70-4C-Y1QE Summary of contents
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... A Microchip Technology Company The SST39WF1601 / SST39WF1602 are a 1M x16 CMOS Multi-Purpose Flash Plus (MPF+) devices manufactured with SST proprietary, high-performance CMOS SuperFlash technology. The split-gate cell design and thick-oxide tunnel- ing injector attain better reliability and manufacturability compared with alternate approaches. The SST39WF1601 / SST39WF1602 write (Program or Erase) with a 1 ...
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... Erase and Pro- gram times increase with accumulated Erase/Program cycles. To meet high density, surface mount requirements, the SST39WF1601/1602 are offered in both 48-ball TFBGA and 48-ball WFBGA packages. See Figures 2 and 3 for pin assignments. ...
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... A Microchip Technology Company Block Diagram Memory Address Figure 1: Functional Block Diagram ©2011 Silicon Storage Technology, Inc. 16 Mbit Multi-Purpose Flash Plus SST39WF1601 / SST39WF1602 X-Decoder Address Buffer Latches CE# OE# WE# Control Logic WP# RESET# 3 Data Sheet SuperFlash Memory Y-Decoder I/O Buffers and Data Latches 1297 B1.0 ...
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... A Microchip Technology Company Block Diagram Figure 2: Pin assignments for 48-ball TFBGA Figure 3: Pin assignments for 48-ball WFBGA ©2011 Silicon Storage Technology, Inc. 16 Mbit Multi-Purpose Flash Plus SST39WF1601 / SST39WF1602 TOP VIEW (balls facing down) 6 A13 A12 A14 A15 A16 A10 A11 DQ7 ...
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... NC No Connection Most significant address for SST39WF1601/1602 MS 19 ©2011 Silicon Storage Technology, Inc. 16 Mbit Multi-Purpose Flash Plus SST39WF1601 / SST39WF1602 Functions To provide memory addresses. During Sector-Erase A -A address lines will select the sector During Block-Erase A -A address lines will select the block Data is internally latched during a Write cycle ...
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... CE# held steadily low, until the first address transition or CE# is driven high. Read The Read operation of the SST39WF1601/1602 is controlled by CE# and OE#, both have to be low for the system to obtain data from the outputs. CE# is used for device selection. When CE# is high, the chip is deselected and only standby power is consumed ...
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... When WP# is low, any attempt to Chip-Erase will be ignored. During the command sequence, WP# should be statically held high or low. Write Operation Status Detection The SST39WF1601/1602 provide two software means to detect the completion of a Write (Program or Erase) cycle, in order to optimize the system write cycle time. The software detection includes two sta- tus bits: Data# Polling (DQ the rising edge of WE#, which initiates the internal Program or Erase operation. The actual completion of the nonvolatile write is asynchronous with the system ...
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... A Microchip Technology Company Data# Polling (DQ When the SST39WF1601/1602 are in the internal Program operation, any attempt to read DQ produce the complement of the true data. Once the Program operation is completed, DQ true data. Note that even though DQ Write operation, the remaining data outputs may still be invalid: valid data on the entire data bus will appear in subsequent successive Read cycles after an interval of 1 µ ...
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... Software Data Protection (SDP) The SST39WF1601/1602 provide the JEDEC approved Software Data Protection scheme for all data alteration operations, i.e., Program and Erase. Any Program operation requires the inclusion of the three-byte sequence. The three-byte load sequence is used to initiate the Program operation, provid- ing optimal protection from inadvertent Write operations, e ...
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... A Microchip Technology Company Common Flash Memory Interface (CFI) The SST39WF1601/1602 contain the CFI information to describe the characteristics of the device. The SST39WF1601/1602 support the original SST CFI Query mode implementation for compatibility with existing SST devices as well as the general CFI Query mode. Both will be explained in subsequent paragraphs ...
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... A Microchip Technology Company Security ID The SST39WF1601/1602 devices offer a 256-bit Security ID space. The Secure ID space is divided into two 128-bit segments - one factory programmed segment and one user programmed segment. The first segment is programmed and locked at SST with a random 128-bit number. The user segment is left un-programmed for the customer to program as desired ...
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... AAH 2AAAH 55H 5555H 5555H AAH 2AAAH 55H 5555H 55H 98H 5555H AAH 2AAAH 55H 5555H XXH F0H -A (Hex can but no other value, for Command sequence for SST39WF1601/1602 but no other value, for Command sequence address lines address lines Address D A OUT IN D ...
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... User ID is read with (Address range = 000008H to 00000FH 0000FFH. Unlocked =0; SST Manufacturer ID = 00BFH, is read with A SST39WF1601 Device ID = BF274BH, is read with A SST39WF1602 Device ID = BF274AH, is read with A 1 Data Data 0051H Query Unique ASCII string “QRY” 0052H 0059H 0002H ...
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... Silicon Storage Technology, Inc. 16 Mbit Multi-Purpose Flash Plus SST39WF1601 / SST39WF1602 Data N 21 Device size = 2 Bytes (15H = 21 MByte) Flash Device Interface description; 0001H = x16-only asynchronous interface Maximum number of byte in multi-byte write = 2 Number of Erase Sector/Block sizes supported by device Sector Information ( Number of sectors ...
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... Outputs shorted for no more than one second. No more than one output shorted at a time. Table 10:Operating Range Range Commercial Industrial Table 11:AC Conditions of Test 1. See Figures 18 and 19 ©2011 Silicon Storage Technology, Inc. 16 Mbit Multi-Purpose Flash Plus SST39WF1601 / SST39WF1602 = 25° 1. Ambient Temp 0°C to +70°C -40°C to +85°C 1 ...
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... This parameter is measured only for initial qualification and after a design or process change that could affect this parameter endurance rating is qualified as a 10,000 cycle minimum for the whole device. A sector- or block-level rating would END result in a higher minimum specification. ©2011 Silicon Storage Technology, Inc. 16 Mbit Multi-Purpose Flash Plus SST39WF1601 / SST39WF1602 = 1.65-1.95V DD Limits Min Max 10 25 ...
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... Software ID Access and Exit Time IDA T Sector-Erase SE T Block-Erase BE T Chip-Erase SCE 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. ©2011 Silicon Storage Technology, Inc. 16 Mbit Multi-Purpose Flash Plus SST39WF1601 / SST39WF1602 = 1.65-1.95V DD Min 500 50 Min ...
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... ADDRESS A 19-0 WE# T OE# CE# DQ 15-0 Note: WP# must be held in proper logic state ( µs prior to and 1µs after the command sequence can be V Figure 5: WE# Controlled Program Cycle Timing Diagram ©2011 Silicon Storage Technology, Inc. 16 Mbit Multi-Purpose Flash Plus SST39WF1601 / SST39WF1602 OLZ CLZ HIGH-Z ...
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... WE# DQ 15-0 Note: WP# must be held in proper logic state (V X can be V Figure 6: CE# Controlled Program Cycle Timing Diagram ADDRESS A 19-0 CE# OE# WE Figure 7: Data# Polling Timing Diagram ©2011 Silicon Storage Technology, Inc. 16 Mbit Multi-Purpose Flash Plus SST39WF1601 / SST39WF1602 5555 2AAA 5555 CPH ...
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... Note: This device also supports CE# controlled Chip-Erase operation. The WE# and CE# signals are interchangeable as long as minimum timings are met. (See Table 17.) WP# must be held in proper logic state (V X can be V Figure 9: WE# Controlled Chip-Erase Timing Diagram ©2011 Silicon Storage Technology, Inc. 16 Mbit Multi-Purpose Flash Plus SST39WF1601 / SST39WF1602 OEH T OE ...
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... The WE# and CE# signals are interchangeable as long as minimum timings are met. (See Table 17 Sector Address X WP# must be held in proper logic state (V X can be V Figure 11:WE# Controlled Sector-Erase Timing Diagram ©2011 Silicon Storage Technology, Inc. 16 Mbit Multi-Purpose Flash Plus SST39WF1601 / SST39WF1602 SIX-BYTE CODE FOR BLOCK-ERASE 5555 2AAA 5555 5555 T WP XXAA ...
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... CE# OE# WE# DQ 15-0 Note: WP# must be held in proper logic state (V X can be V Figure 13:CFI Query Entry and Read ©2011 Silicon Storage Technology, Inc. 16 Mbit Multi-Purpose Flash Plus SST39WF1601 / SST39WF1602 Three-Byte Sequence for Software ID Entry 5555 2AAA 5555 IDA T WPH XXAA ...
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... CE# OE# WE# DQ 15-0 Note: WP# must be held in proper logic state (V X can be V Figure 15:Sec ID Entry ©2011 Silicon Storage Technology, Inc. 16 Mbit Multi-Purpose Flash Plus SST39WF1601 / SST39WF1602 THREE-BYTE SEQUENCE FOR SOFTWARE ID EXIT AND RESET 5555 2AAA 5555 XXAA XX55 XXF0 T IDA ...
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... A Microchip Technology Company RST# CE#/OE# Figure 16:RST# Timing Diagram (When no internal operation is in progress) RST# CE#/OE# Figure 17:RST# Timing Diagram (During Program or Erase operation) ©2011 Silicon Storage Technology, Inc. 16 Mbit Multi-Purpose Flash Plus SST39WF1601 / SST39WF1602 RHR End-of-Write Detection (Toggle-Bit) 24 Data Sheet 1297 F22 ...
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... V and fall times (10% Figure 18:AC Input/Output Reference Waveforms Figure 19:A Test Load Example ©2011 Silicon Storage Technology, Inc. 16 Mbit Multi-Purpose Flash Plus SST39WF1601 / SST39WF1602 V INPUT REFERENCE POINTS IT (0 for a logic “1” and V ...
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... A Microchip Technology Company Note: X can be V Figure 20:Word-Program Algorithm ©2011 Silicon Storage Technology, Inc. 16 Mbit Multi-Purpose Flash Plus SST39WF1601 / SST39WF1602 Start Load data: XXAAH Address: 5555H Load data: XX55H Address: 2AAAH Load data: XXA0H Address: 5555H Load Word Address/Word Data Wait for end of ...
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... A Microchip Technology Company Internal Timer Program/Erase Initiated Wait SCE Program/Erase Completed Figure 21:Wait Options ©2011 Silicon Storage Technology, Inc. 16 Mbit Multi-Purpose Flash Plus SST39WF1601 / SST39WF1602 Toggle Bit Program/Erase Initiated Read word Read same No word No Does DQ 6 match Yes Program/Erase Completed 27 Data Sheet ...
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... Address: 55H Wait T IDA Read CFI data Note: X can be V Figure 22:Software ID/CFI Entry Command Flowcharts ©2011 Silicon Storage Technology, Inc. 16 Mbit Multi-Purpose Flash Plus SST39WF1601 / SST39WF1602 CFI Query Entry Command Sequence Command Sequence Load data: XXAAH Address: 5555H Load data: XX55H ...
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... A Microchip Technology Company Note: X can be V Figure 23:Software ID/CFI Exit Command Flowcharts ©2011 Silicon Storage Technology, Inc. 16 Mbit Multi-Purpose Flash Plus SST39WF1601 / SST39WF1602 Software ID Exit/CFI Exit/Sec ID Exit Command Sequence Load data: XXAAH Address: 5555H Load data: XX55H Address: 2AAAH Load data: XXF0H ...
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... Load data: XX10H Address: 5555H Wait T SCE Chip erased Note: X can be V Figure 24:Erase Command Sequence ©2011 Silicon Storage Technology, Inc. 16 Mbit Multi-Purpose Flash Plus SST39WF1601 / SST39WF1602 Sector-Erase Command Sequence Load data: XXAAH Address: 5555H Load data: XX55H Address: 2AAAH Load data: XX80H ...
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... A Microchip Technology Company Product Ordering Information SST 39 WF 1602 XX XX Valid Combinations for SST39WF1601 SST39WF1601-70-4C-B3KE SST39WF1601-70-4I-B3KE Valid Combinations for SST39WF1602 SST39WF1602-70-4C-B3KE SST39WF1602-70-4I-B3KE Note:Valid combinations are those products in mass production or will be in mass production. Consult your SST sales representative to confirm availability of valid combinations and to determine availability of new combi- nations. © ...
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... Coplanarity: 0. Ball opening size is 0. 0.05 mm) Figure 25:48-ball Thin-Profile, Fine-pitch Ball Grid Array (TFBGA) 6mm x 8mm SST Package Code: B3K ©2011 Silicon Storage Technology, Inc. 16 Mbit Multi-Purpose Flash Plus SST39WF1601 / SST39WF1602 TOP VIEW 8.00 0.10 6.00 0.10 1.10 0.10 SIDE VIEW ...
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... A1 CORNER SEATING PLANE Note: Figure 26:48-ball Very-Very-Thin-Profile, Fine-pitch Ball Grid Array (WFBGA) 4mm x 6mm SST Package Code MAQ ©2011 Silicon Storage Technology, Inc. 16 Mbit Multi-Purpose Flash Plus SST39WF1601 / SST39WF1602 TOP VIEW 6.00 0.08 4.00 0. 0.73 max. 0.636 nom. DETAIL 0.08 0.20 0.06 1 ...
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... Added YIQE package 04 • Changed 000010H to 000017H to 000008H to 00000FH three places in footnotes of Table 6 on page 12. 05 • EOL of SST39WF1601-70-4C-Y1QE, SST39WF1601-70-4I-Y1QE, SST39WF1602-70-4C-Y1QE, and SST39WF1602-70-4I-Y1QE. Replacement parts SST39WF1601-70-4C-MAQE, SST39WF1601-70-4I- MAQE, SST39WF1602-70-4C-MAQE, and SST39WF1602-70-4I-MAQE in this document. • Added MAQE package drawing and information. • ...