DS1803E-010 Maxim Integrated Products, DS1803E-010 Datasheet - Page 8
![IC POT DUAL ADDRESS 10K 14-TSSOP](/photos/6/57/65725/406-14-tssop_sml.jpg)
DS1803E-010
Manufacturer Part Number
DS1803E-010
Description
IC POT DUAL ADDRESS 10K 14-TSSOP
Manufacturer
Maxim Integrated Products
Datasheet
1.DS18030-010.pdf
(11 pages)
Specifications of DS1803E-010
Taps
256
Resistance (ohms)
10K
Number Of Circuits
2
Temperature Coefficient
750 ppm/°C Typical
Memory Type
Volatile
Interface
I²C, 2-Wire Serial
Voltage - Supply
2.7 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
14-TSSOP
Resistance In Ohms
10K
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
DS1803E010
Available stocks
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Part Number
Manufacturer
Quantity
Price
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Part Number:
DS1803E-010+
Manufacturer:
Maxim
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5. After this period, the first clock pulse is generated.
6. A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the
7. The maximum t
8. A fast mode device can be used in a standard mode system, but the requirement t
9. C
10. Typical values are for t
11. -3 dB cutoff frequency characteristics for the DS1803 depend on potentiometer total resistance:
12. Address Inputs, A0, A1, and A2, should be tied to either V
13. Absolute linearity is used to determine wiper voltage versus expected voltage as determined by wiper
14. Relative linearity is used to determine the change in voltage between successive tap positions. Device
15. Fast mode.
16. Standard mode.
17. Valid at 25°C only.
V
SCL signal.
then be met. This will automatically be the case if the device does not stretch the LOW period of the
SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next
data bit to the SDA line t
DS1803-010; 1 MHz, DS1803-50; 200 kHz, DS1803-100; 100 kHz.
address selections.
position. Device test limits are ±1.6 LSB.
test limits ±0.5 LSB.
B
IHMIN
- total capacitance of one bus line in picofarads, timing referenced to (0.9)(V
of the SCL signal) in order to bridge the undefined region of the falling edge of SCL.
HD:DAT
has only to be met if the device does not stretch the LOW period (t
A
= 25°C and nominal supply voltage.
RMAX
+ t
SU:DAT
= 1000 + 250=1250 ns before the SCL line is released.
8 of 11
CC
or GND depending on the desired
CC
SU:DAT
) and (0.1)(V
> 250 ns must
LOW
) of the
CC
).