UDA1334ATS/N2,112 NXP Semiconductors, UDA1334ATS/N2,112 Datasheet - Page 8

• Manufacturer Part Number: UDA1334ATS/N2,112
• Description: IC AUDIO DAC LP 16-SSOP
• Manufacturer: NXP Semiconductors

Specifications of UDA1334ATS/N2,112

• Number Of Converters: 2
• Package / Case: 16-SSOP
• Number Of Bits: 24
• Data Interface: Serial
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Interface Type: Serial
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2.4 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power Dissipation (max): -
• Settling Time: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-3443-5; 935266839112; UDA1334ATSDH

NXP Semiconductors
8.4
The FSDAC is a semi-digital reconstruction filter that
converts the 1-bit data stream of the noise shaper to an
analog output voltage. The filter coefficients are
implemented as current sources and are summed at virtual
ground of the output operational amplifier. In this way very
high signal-to-noise performance and low clock jitter
sensitivity is achieved. No post filter is needed due to the
inherent filter function of the DAC. On-board amplifiers
convert the FSDAC output current to an output voltage
signal capable of driving a line output.
The output voltage of the FSDAC scales proportionally to
the power supply voltage.
2000 Jul 31
handbook, halfpage
Low power audio DAC with PLL
Filter stream DAC
3.0 V
V ref(DAC)
Fig.3 Power-on reset circuit.
C1 >
10 μF
V DDA
13
12
50 kΩ
50 kΩ
UDA1334ATS
CIRCUIT
RESET
MGT015
8
8.5
The UDA1334ATS has an internal Power-on reset circuit
(see Fig.3) which resets the test control block.
The reset time (see Fig.4) is determined by an external
capacitor which is connected between pin V
ground. The reset time should be at least 1 μs for
V
will be reset again for V
During the reset time the system clock should be running.
handbook, halfpage
ref(DAC)
V ref(DAC)
V DDD
V DDA
(V)
(V)
(V)
1.25
0.75
1.5
1.5
1.5
Power-on reset
3.0
3.0
3.0
0
0
0
< 1.25 V. When V
Fig.4 Power-on reset timing.
>1 μs
ref(DAC)
DDA
is switched off, the device
< 0.75 V.
UDA1334ATS
Product specification
ref(DAC)
MGL984
and
t
t
t