CS4391A-KZZ Cirrus Logic Inc, CS4391A-KZZ Datasheet - Page 22

• Manufacturer Part Number: CS4391A-KZZ
• Description: IC DAC 24BIT 192KHZ W/VC 20TSSOP
• Manufacturer: Cirrus Logic Inc

Specifications of CS4391A-KZZ

• Data Interface: Serial
• Number Of Bits: 24
• Number Of Converters: 2
• Voltage Supply Source: Analog and Digital
• Power Dissipation (max): 175mW
• Operating Temperature: -10°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 20-TSSOP
• Resolution (bits): 24bit
• Sampling Rate: 192kSPS
• Input Channel Type: Serial
• Supply Voltage Range - Analog: 4.75V To 5.25V
• Supply Current: 17mA
• Digital Ic Case Style: TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Settling Time: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 598-1064-5

5.
Reset - RST
Interface Power - VL
Serial Audio Data - SDATA
22
Pin 1, Input
Function:
Pin 2, Input
Function:
Pin 3, Input
Function:
PIN DESCRIPTION - PCM DATA MODE
Left/Right Clock
See Description
See Description (SCL/CCLK) M2
See Description (SDA/CDIN) M1
See Description
Hardware Mode: The device enters a low power mode and the internal state machine is reset to the de-
fault setting when low. When high, the device becomes operational.
Control Port Mode: The device enters a low power mode and all internal registers are reset to the default
settings, including the control port, when low. When high, the control port becomes operational and the
PDN bit must be cleared before normal operation will occur. The control port can not be accessed when
reset is low. The Control Port Enable Bit must also be enabled after a device reset.
RST is required to remain low until the power supplies and clocks are applied and stable.
Digital interface power supply. The voltage on this pin determines the logic level high threshold for the
digital inputs.
Two's complement MSB-first serial data is input on this pin. The data is clocked into SDATA via the serial
clock and the channel is determined by the Left/Right clock. The required relationship between the
Left/Right clock, serial clock and serial data is defined by the Mode Control Byte in Control Port Mode or
the Mode Pins in Hardware Mode. The options are detailed in Figures 7-24.
Logic Voltage
Master Clock
Serial Clock
Serial Data
Reset
(AD0/CS) M0
SDATA
MCLK
LRCK
SCLK
RST
M3
VL
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
AMUTEC
AOUTA-
AOUTA+
VA
AGND
AOUTB+
AOUTB-
BMUTEC
CMOUT
FILT+
Channel A Mute Control
Differential Output
Differential Output
Analog Power
Analog Ground
Differential Output
Differential Output
Channel B Mute Control
Common Mode Voltage
Positive Voltage Reference
CS4391A
DS600PP3