CS4391A-KZZ Cirrus Logic Inc, CS4391A-KZZ Datasheet - Page 23

• Manufacturer Part Number: CS4391A-KZZ
• Description: IC DAC 24BIT 192KHZ W/VC 20TSSOP
• Manufacturer: Cirrus Logic Inc

Specifications of CS4391A-KZZ

• Data Interface: Serial
• Number Of Bits: 24
• Number Of Converters: 2
• Voltage Supply Source: Analog and Digital
• Power Dissipation (max): 175mW
• Operating Temperature: -10°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 20-TSSOP
• Resolution (bits): 24bit
• Sampling Rate: 192kSPS
• Input Channel Type: Serial
• Supply Voltage Range - Analog: 4.75V To 5.25V
• Supply Current: 17mA
• Digital Ic Case Style: TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Settling Time: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 598-1064-5

Serial Clock - SCLK
Left / Right Clock - LRCK
Master Clock - MCLK
Mode Select - M3, M2, M1 and M0 (Stand-alone Mode)
Mode Select - M3 (Control Port Mode)
DS600PP3
Pin 4, Input
Function:
Pin 5, Input
Function:
Pin 6, Input
Function:
Pins 7, 8, 9 and 10 Inputs
Function:
Pin 7, Input
Function:
Clocks the individual bits of the serial data into the SDATA pin. The required relationship between the
Left/Right clock, serial clock and serial data is defined by the Mode Control Byte in Control Port Mode or
the Mode pins in Hardware Mode. The options are detailed in Figures 7-24.
The Left / Right clock determines which channel is currently being input on the serial audio data input,
SDATA. The frequency of the Left/Right clock must be at the input sample rate. Audio samples in
Left/Right sample pairs will be simultaneously output from the digital-to-analog converter whereas
Right/Left pairs will exhibit a one sample period difference. The required relationship between the
Left/Right clock, serial clock and serial data is defined by the Mode Control Byte in Control Port Mode or
the Mode pins in Stand-alone Mode. The options are detailed in Figures 7-24.
The master clock frequency must be either 256x, 384x, 512x, 768x or 1024x the input sample rate in Sin-
gle Speed Mode; either 128x, 192x 256x, 384x or 512x the input sample rate in Double Speed Mode; or
64x, 96x 128x, 192x or 256 x the input sample rate in Quad Speed Mode. Tables 8-10 illustrate the stan-
dard audio sample rates and the required master clock frequencies.
Note: These clocking ratios are only available in Control Port Mode when the MCLK Divide bit is enabled.
The Mode Select Pins, M0-M3, select the operational mode of the device as detailed in Tables 11-15.
The Mode Select Pin, M3, is not used in PCM Control Port mode and should be terminated to ground.
CS4391A
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