HI5731BIB Intersil, HI5731BIB Datasheet - Page 3

• Manufacturer Part Number: HI5731BIB
• Description: IC DAC 12-BIT 100MSPS 28-SOIC
• Manufacturer: Intersil

Specifications of HI5731BIB

• Settling Time: 20ns
• Number Of Bits: 12
• Data Interface: Parallel
• Number Of Converters: 1
• Voltage Supply Source: Analog and Digital, Dual ±
• Power Dissipation (max): 650mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 28-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Absolute Maximum Ratings
Digital Supply Voltage V
Negative Digital Supply Voltage DV
Negative Analog Supply Voltage AV
Digital Input Voltages (D11-D0, CLK) to DGND. . . . . DV
Internal Reference Output Current. . . . . . . . . . . . . . . . . . . . ±2.5mA
Voltage from CTRL IN to AV
Control Amplifier Output Current . . . . . . . . . . . . . . . . . . . . . ±2.5mA
Reference Input Voltage Range . . . . . . . . . . . . . . . . . .-3.7V to AV
Analog Output Current (I
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . -40
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
Electrical Specifications
SYSTEM PERFORMANCE
Resolution
Integral Linearity Error, INL
Differential Linearity Error, DNL
Offset Error, I
Full Scale Gain Error, FSE
Full Scale Gain Drift
Offset Drift Coefficient
Full Scale Output Current, I
Output Voltage Compliance Range
DYNAMIC CHARACTERISTICS
Throughput Rate
Output Voltage Full Scale Step
Settling Time, t
Singlet Glitch Area, GE (Peak)
Doublet Glitch Area, (Net)
Output Slew Rate
Output Rise Time
Output Fall Time
Spurious Free Dynamic Range within a Window
(Note 3)
1. θ
JA
is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
OS
SETT
PARAMETER
, Full Scale
CC
OUT
to DGND . . . . . . . . . . . . . . . . . . . +5.5V
EE
FS
) . . . . . . . . . . . . . . . . . . . . . . . . . 30mA
. . . . . . . . . . . . . . . . . . . . 2.5V to 0V
3
EE
EE
AV
T
A
to DGND . . . . . . . . . . -5.5V
EE
= 25
to AGND, ARTN . . . . . -5.5V
, DV
o
C for All Typical Values
EE
= -4.94 to -5.46V, V
(Note 4) (“Best Fit” Straight Line)
(Note 4)
(Note 4)
(Notes 2, 4)
With Internal Reference
(Note 3)
(Note 3)
(Note 3)
To ±0.5 LSB Error Band R
(Note 3)
R
R
R
R
f
f
f
f
f
f
CLK
CLK
CLK
CLK
CLK
CLK
L
L
L
L
= 50Ω, DAC Operating in Latched Mode (Note 3)
= 50Ω, DAC Operating in Latched Mode (Note 3)
= 50Ω, DAC Operating in Latched Mode (Note 3)
= 50Ω (Note 3)
CC
o
C to 85
= 10MSPS, f
= 20MSPS, f
= 40MSPS, f
= 50MSPS, f
= 80MSPS, f
= 100MSPS, f
to -0.5V
EE
o
C
HI5731
CC
TEST CONDITIONS
OUT
OUT
OUT
OUT
OUT
= +4.75 to +5.25V, V
OUT
= 1.23MHz, 2MHz Span
= 5.055MHz, 2MHz Span
= 16MHz, 10MHz Span
= 10.1MHz, 2MHz Span
= 5.1MHz, 2MHz Span
= 10.1MHz, 2MHz Span
Thermal Information
Thermal Resistance (Typical, Note 1)
Maximum Junction Temperature
Maximum Storage Temperature Range . . . . . . . . . . -65
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300
L
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
HI5731BIx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150
(SOIC - Lead Tips Only)
= 50Ω
REF
= Internal
-1.25
MIN
100
T
12
A
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
= -40
HI5731BI
20.48
1,000
±150
TYP
0.75
o
675
470
0.5
20
20
85
77
75
80
78
79
C TO 85
1
5
3
-
-
-
-
MAX
0.05
1.5
1.0
o
75
10
0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
C
o
θ
C to 150
JA
FSR/
UNITS
MSPS
µA/
pV-s
pV-s
V/µs
LSB
LSB
ppm
(
Bits
dBc
dBc
dBc
dBc
dBc
dBc
50
70
mA
µA
ns
ps
ps
o
%
V
C/W)
o
o
C
C
o
o
o
C
C
C