MAX5556ESA+ Maxim Integrated Products, MAX5556ESA+ Datasheet - Page 15

• Manufacturer Part Number: MAX5556ESA+
• Description: IC DAC STEREO AUDIO 8-SOIC
• Manufacturer: Maxim Integrated Products

Specifications of MAX5556ESA+

• Number Of Bits: 16
• Data Interface: Serial
• Number Of Converters: 2
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• Number Of Dac Outputs: 2
• Resolution: 16 bit
• Interface Type: Serial (3-Wire)
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 4.75 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Maximum Power Dissipation: 471 mW
• Minimum Operating Temperature: - 40 C
• Supply Current: 13 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power Dissipation (max): -
• Settling Time: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

The MAX5556 mutes both outputs after detecting one
of four invalid clock conditions. The device mutes its
output to prevent propagation of pops, clicks, or cor-
rupted data through the signal path. The MAX5556
forces the outputs to the quiescent DC voltage (2.4V) to
prevent clicks in capacitive-coupled systems. Invalid
clock conditions include:
When the MCLK/LRCLK ratio returns to 256, 384, or
512 and MCLK is equal or greater than its minimum
operating frequency, the MAX5556 output returns to its
full-scale setting over a soft-start mute time of 20ms
(Figure 12).
When the positive supply is removed from the
MAX5556, the output discharges to ground. When
power is restored, the power-up ramp routine engages
once a valid clock ratio is established (see the Power-
Up section).
Avoid violating absolute maximum conditions by sup-
plying digital inputs to the part or forcing voltages on
the analog outputs during a loss-of-power event.
Connect the MAX5556 output through a passive output
filter as detailed in Figure 8 for a low-cost solution. This
lowpass filter yields single-pole (20dB/decade) roll-off
at a corner frequency (f
In the case of Figure 8, f
1) MCLK/LRCLK ratio changes between 256, 384,
2) Transition between internal and external serial-
3) Invalid MCLK/LRCLK ratio
4) MCLK falls below the minimum operating
and 512
clock mode
frequency 2kHz
Loss of Clock and Invalid Clock Conditions
Applications Information
Low-Cost Line-Level Solution
______________________________________________________________________________________
f
C
C
C
) determined by:
=
is approximately 190kHz.
2π
1
RC
Power-Down
Low-Cost Stereo Audio DAC
For enhanced performance, connect the MAX5556
output to an active filter by using an operational amplifi-
er as shown in Figure 9. The use of an active filter allows
for steeper roll-off, more efficient filtering, and also adds
the capability of a programmable output gain.
For correct power-up sequencing, apply V
connect the input digital signals. Do not apply digital sig-
nals before V
Do not violate any of the absolute maximum ratings by
removing power with the digital inputs still connected.
To correctly power down the device, first disconnect
the digital input signals, and then remove V
Proper layout and grounding are essential for optimum
performance. Use large traces for the power-supply
inputs and analog outputs to minimize losses due to
parasitic trace resistance. Large traces also aid in mov-
ing heat away from the package. Proper grounding
improves audio performance, minimizes crosstalk
between channels, and prevents any switching noise
from coupling into the audio signal. Route the analog
paths (GND, V
digital signals. Connect a 0.1µF capacitor in parallel
with a 4.7µF capacitor as close to V
ESR-type capacitors are recommended for supply
decoupling applications. A small value C0G-type
bypass capacitor located as close to the device as
possible is recommended in parallel with larger values.
Power-Supply Connections and Ground
High-Performance Line-Level Solution
DD
DD
is applied.
, OUTL, and OUTR) away from the
Power-Supply Sequencing
DD
Management
as possible. Low
DD
DD
.
and then
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