MAX5556ESA+ Maxim Integrated Products, MAX5556ESA+ Datasheet - Page 4

• Manufacturer Part Number: MAX5556ESA+
• Description: IC DAC STEREO AUDIO 8-SOIC
• Manufacturer: Maxim Integrated Products

Specifications of MAX5556ESA+

• Number Of Bits: 16
• Data Interface: Serial
• Number Of Converters: 2
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• Number Of Dac Outputs: 2
• Resolution: 16 bit
• Interface Type: Serial (3-Wire)
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 4.75 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Maximum Power Dissipation: 471 mW
• Minimum Operating Temperature: - 40 C
• Supply Current: 13 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power Dissipation (max): -
• Settling Time: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Low-Cost Stereo Audio DAC
ELECTRICAL CHARACTERISTICS (continued)
Note 1: 100% production tested at T
Note 2: 0.5 LSB of triangular PDF dither added to data.
Note 3: Guaranteed by design, not production tested.
Note 4: PSRR test block diagram shown in Figure 1 denotes the test setup used to measure PSRR.
Note 5: Volume ramping interval starts from establishment of a valid MCLK to LRCLK ratio. Total time is proportional to the sample
Note 6: In external SCLK mode, LRCLK duty cycles are not limited, provided all data formatting requirements are met. See Figure 4.
Note 7: The LRCLK duty cycle must be 50% ±1/2 MCLK period in internal SCLK mode.
Note 8: The SCLK/LRCLK ratio can be set to 32, 48, or 64, depending on the MCLK/LRCLK ratio selected. See Figure 4.
Figure 1. PSRR Test Block Diagram
4
(V
= 12.288MHz, measurement bandwidth 10Hz to 20kHz, T
values at V
INTERNAL SCLK MODE
LRCLK Duty Cycle
Internal SCLK Period
LRCLK Edge to Internal SCLK
SDATA Valid to Internal SCLK
Rising Setup Time
DD
(100mV
DC POWER SUPPLY
_______________________________________________________________________________________
AUDIO SIGNAL
= +4.75V to +5.5V, V
GENERATOR
(5VDC)
rate (f
P-P
PARAMETER
DD
AT 1kHz)
S
= +5V, T
). 20ms based on 48ksps operation.
A
= +25°C.) (Note 1)
Z
+
GND
G
= 0V, R
A
SYMBOL
t
= +85°C. Limits to -40°C are guaranteed by design.
t
ISCLKR
OUT
t
ISCLK
t
ISDH
ISDS
_ = 10kΩ, C
(Note 7)
(Note 8)
MCLK period = t
LRCLK
MCLK
SCLK
SDATA
OUT
A
_ = 10pF, 0dBFS sine-wave signal at 997Hz, f
= -40°C to +85°C, outputs are unloaded, unless otherwise noted. Typical
CONDITIONS
MCLK
MAX5556
GND
V
DD
t
LOUT, ROUT
MCLK
1/f
t
MCLK
MIN
SCLK
+ 10
t
LRCLK
ISCLK
TYP
50
/2
(f
S
) = 48kHz, f
MAX
SPECTRUM
ANALYZER
UNITS
MCLK
ns
ns
ns
%