MAX5556ESA+ Maxim Integrated Products, MAX5556ESA+ Datasheet - Page 3

• Manufacturer Part Number: MAX5556ESA+
• Description: IC DAC STEREO AUDIO 8-SOIC
• Manufacturer: Maxim Integrated Products

Specifications of MAX5556ESA+

• Number Of Bits: 16
• Data Interface: Serial
• Number Of Converters: 2
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• Number Of Dac Outputs: 2
• Resolution: 16 bit
• Interface Type: Serial (3-Wire)
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 4.75 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Maximum Power Dissipation: 471 mW
• Minimum Operating Temperature: - 40 C
• Supply Current: 13 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power Dissipation (max): -
• Settling Time: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

ELECTRICAL CHARACTERISTICS (continued)
(V
12.288MHz, measurement bandwidth 10Hz to 20kHz, unless otherwise specified. T
Outputs are unloaded, unless otherwise noted. Typical values at V
DC CHARACTERISTICS
Interchannel Gain Mismatch
Gain Error
Gain Drift
ANALOG OUTPUTS
Full-Scale Output Voltage
DC Quiescent Output Voltage
Minimum Load Resistance
Maximum Load Capacitance
Power-Supply Rejection Ratio
POP AND CLICK SUPPRESSION
Mute Attenuation
Power-Up Until Bias Established
Valid Clock to Normal Operation
DIGITAL AUDIO INTERFACE (SCLK, SDATA, MCLK, LRCLK)
Input-Voltage High
Input-Voltage Low
Input Leakage Current
Input Capacitance
TIMING CHARACTERISTICS
Input Sample Rate
MCLK Pulse-Width Low
MCLK Pulse-Width High
EXTERNAL SCLK MODE
LRCLK Duty Cycle
SCLK Pulse-Width Low
SCLK Pulse-Width High
SCLK Period
LRCLK Edge to SCLK Rising
LRCLK Edge to SCLK Rising
SDATA Valid to SCLK Rising
SCLK Rising to SDATA Hold Time
DD
= +4.75V to +5.5V, GND = 0V, R
PARAMETER
_______________________________________________________________________________________
V
OU T R
SYMBOL
OUT
PSRR
t
t
t
t
MCLKH
MCLKL
SCLKH
SCLKL
t
t
t
t
t
V
C
SCLK
SLRS
SLRH
R
V
SDH
V
SDS
, V
I
f
Q
IN
L
L
IH
S
_ = 10kΩ, C
IL
OU T L
Input code = 0
V
Figure 14
Soft-start ramp time, Figure 15 (Note 5)
MCLK/LRCLK = 512
MCLK/LRCLK = 384
MCLK/LRCLK = 256
MCLK/LRCLK = 512
MCLK/LRCLK = 384
MCLK/LRCLK = 256
(Note 6)
RIPPLE
Low-Cost Stereo Audio DACs
OUT
_ = 10pF, 0dBFS sine-wave signal at 997Hz, f
= 100mV
CONDITIONS
DD
P-P
= +5V, T
, frequency = 1kHz
A
= +25°C.) (Note 1)
A
= -40°C to +85°C, unless otherwise noted.
1 / (128
MIN
3.25
x f
-10
2.0
10
20
20
10
20
20
25
20
20
20
20
20
20
-5
2
S
)
LRCLK
TYP
100
100
100
360
0.1
3.5
2.4
66
20
3
8
(f
S
) = 48kHz, f
MAX
3.75
+10
0.4
0.8
+5
50
75
ppm/°C
UNITS
MCLK
V
kHz
dB
kΩ
dB
dB
ms
ms
pF
µA
pF
ns
ns
ns
ns
ns
ns
ns
ns
ns
%
%
P-P
V
V
V
=
3