MAX5531ETC+ Maxim Integrated Products, MAX5531ETC+ Datasheet - Page 5

• Manufacturer Part Number: MAX5531ETC+
• Description: IC DAC 12BIT SGL ULP 12-TQFN
• Manufacturer: Maxim Integrated Products

Specifications of MAX5531ETC+

• Settling Time: 660µs
• Number Of Bits: 12
• Data Interface: MICROWIRE™, QSPI™, Serial, SPI™
• Number Of Converters: 1
• Voltage Supply Source: Single Supply
• Power Dissipation (max): 1.35mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 12-TQFN Exposed Pad
• Number Of Dac Outputs: 1
• Resolution: 12 bit
• Interface Type: Serial (SPI)
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 1.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Supply Current: 0.007 mA
• Voltage Reference: Internal
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

TIMING CHARACTERISTICS
(V
TIMING CHARACTERISTICS
(V
Note 1: Linearity is tested within codes 96 to 4080.
Note 2: Offset is tested at code 96.
Note 3: Gain is tested at code 4095. FB is connected to OUT.
Note 4: Guaranteed by design. Not production tested.
Note 5: V
Note 6: Outputs can be shorted to V
Note 7: Optimal noise performance is at 2nF load capacitance.
Note 8: Thermal hysteresis is defined as the change in the initial +25°C output voltage after cycling the device from T
Note 9: All digital inputs at V
Note 10: Load = 10kΩ in parallel with 100pF, V
TIMING CHARACTERISTICS (V
Serial Clock Frequency
DIN to SCLK Rise Setup Time
DIN to SCLK Rise Hold Time
SCLK Pulse-Width High
SCLK Pulse-Width Low
CS Pulse-Width High
SCLK Rise to CS Rise Hold Time
CS Fall to SCLK Rise Setup Time
SCLK Fall to CS Fall Setup
CS Rise to SCK Rise Hold Time
TIMING CHARACTERISTICS (V
Serial Clock Frequency
DIN to SCLK Rise Setup Time
DIN to SCLK Rise Hold Time
SCLK Pulse-Width High
SCLK Pulse-Width Low
CS Pulse-Width High
SCLK Rise to CS Rise Hold Time
CS Fall to SCLK Rise Setup Time
SCLK Fall to CS Fall Setup
CS Rise to SCK Rise Hold Time
DD
DD
= +4.5V to +5.5V, T
= +1.8V to +5.5V, T
DD
PARAMETER
PARAMETER
must be a minimum of 1.8V.
_______________________________________________________________________________________
A
A
= T
= T
DD
MIN
MIN
or GND.
DD
DD
to T
to T
DD
= 4.5V TO 5.5V)
= 1.8V TO 5.5V)
SYMBOL
SYMBOL
MAX
MAX
f
f
or GND indefinitely, provided that the package power dissipation is not exceeded.
t
t
t
t
t
SCLK
t
t
SCLK
t
t
t
CSW
CSW
t
t
CSO
t
t
CSH
CSO
t
t
CSH
CSS
t
t
CSS
CS1
CS1
DH
CH
DH
CH
DS
CL
DS
CL
, unless otherwise noted. Typical values are at T
, unless otherwise noted. Typical values are at T
DD
= 5V, V
REF
= 4.096V (MAX5530) or V
CONDITIONS
CONDITIONS
Ultra-Low-Power, 12-Bit,
Voltage-Output DACs
REF
A
A
= 3.9V (MAX5531).
= +25°C.)
= +25°C.)
MIN
MIN
150
100
24
40
40
30
30
15
24
24
20
20
0
0
0
0
0
0
0
0
TYP
TYP
MAX
MAX
16.7
MAX
10
to T
UNITS
UNITS
MIN
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
.
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