AD5504BRUZ Analog Devices Inc, AD5504BRUZ Datasheet - Page 9

• Manufacturer Part Number: AD5504BRUZ
• Description: IC DAC 12BIT SPI 16-TSSOP
• Manufacturer: Analog Devices Inc

Specifications of AD5504BRUZ

• Data Interface: SPI™, QSPI™, MICROWIRE™, and DSP
• Design Resources: Powering a 30V DAC from a 3V supply (CN0193)
• Settling Time: 45µs
• Number Of Bits: 12
• Number Of Converters: 4
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 16-TSSOP
• Resolution (bits): 12bit
• Input Channel Type: Serial
• Supply Voltage Range - Analogue: 10V To 62V
• Supply Voltage Range - Digital: 2.3V To 5.5V
• Supply Current: 2mA
• Digital Ic: RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power Dissipation (max): -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Table 7. Pin Function Descriptions
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
AGND
Mnemonic
CLR
SYNC
SCLK
SDI
SDO
DGND
LDAC
V
V
V
V
R_SEL
V
ALARM
V
OUTD
OUTC
OUTB
OUTA
DD
LOGIC
Description
Asynchronous Clear Input. The CLR input is falling edge sensitive. When CLR is low, all LDAC pulses are ignored.
When CLR is activated, the input register and the DAC register are set to 0x000 and the outputs to zero scale.
Falling Edge Synchronization Signal. This is the frame synchronization signal for the input data. When SYNC
goes low, it enables the input shift register and data is transferred in on the falling edges of the following
clocks. The selected DAC register is updated after the 16th clock cycle, unless SYNC is taken high before this
edge, in which case the rising edge of SYNC acts as an interrupt, and the write sequence is ignored by the DAC.
Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data
can be transferred at rates up to 16 MHz.
Serial Data Input. This part has a 16-bit shift register. Data is clocked into the register on the falling edge of the
serial clock input.
Serial Data Output. CMOS output. This pin serves as the readback function for all DAC and control registers.
Data is clocked out on the rising edge of SCLK and is valid on the falling edge of SCLK.
Digital Ground Pin.
Analog Ground Pin.
Load DAC Input. Pulsing this pin low allows any or all DAC registers to be updated if the input registers have
new data. This allows all DAC outputs to update simultaneously. Alternatively, this pin can be tied permanently
low.
Buffered Analog Output Voltage from DAC D.
Buffered Analog Output Voltage from DAC C.
Buffered Analog Output Voltage from DAC B.
Buffered Analog Output Voltage from DAC A.
Range Select Pin. Tying this pin to DGND selects a DAC output range of 0 V to 60 V, alternatively tying R_SEL to
V
Positive Analog Power Supply. 10 V to 62 V for the specified performance. This pin should be decoupled with
0.1 μF ceramic capacitors and 10 μF capacitors.
Active Low CMOS Output Pin. This pin flags an alarm if the temperature on the die exceeds 110°C.
Logic Power Supply; 2.3 V to 5.5 V. Decouple this pin with 0.1μF ceramic capacitors and 10 μF capacitors.
LOGIC
selects a DAC output range of 0 V to 30 V.
DGND
AGND
SYNC
LDAC
SCLK
SDO
CLR
SDI
Figure 5. TSSOP Configuration
1
2
3
4
5
6
7
8
Rev. 0 | Page 9 of 20
(Not to Scale)
AD5504
TOP VIEW
16
15
14
13
12
11
10
9
V
ALARM
V
R_SEL
V
V
V
V
LOGIC
DD
OUTA
OUTB
OUTC
OUTD
AD5504