CS4346-CZZ Cirrus Logic Inc, CS4346-CZZ Datasheet - Page 14
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CS4346-CZZ
Manufacturer Part Number
CS4346-CZZ
Description
IC DAC 24BIT 192KHZ 10-TSSOP
Manufacturer
Cirrus Logic Inc
Datasheet
1.CS4344-CZZ.pdf
(24 pages)
Specifications of CS4346-CZZ
Data Interface
Serial
Number Of Bits
24
Number Of Converters
2
Voltage Supply Source
Single Supply
Power Dissipation (max)
150mW
Operating Temperature
-10°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
10-TSSOP
Resolution (bits)
24bit
Sampling Rate
192kSPS
Input Channel Type
Serial
Supply Current
22mA
Digital Ic Case Style
TSSOP
No. Of Pins
10
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Settling Time
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
598-1053-5
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
14
Right Justified, 24-Bit Data
INT SCLK = 64 Fs if
MCLK/LRCK = 1024, 512, 256, 128, or 64
INT SCLK = 48 Fs if
MCLK/LRCK = 768, 384, 192, or 96
INT SCLK = 72 Fs if
MCLK/LRCK = 1152
Right Justified, 16-Bit Data
INT SCLK = 32 Fs if
MCLK/LRCK = 1024, 512, 256, 128, or 64
INT SCLK = 48 Fs if
MCLK/LRCK = 768, 384, 192, or 96
INT SCLK = 72 Fs if
MCLK/LRCK = 1152
SDATA
SDATA
LRCK
LRCK
SCLK
SCLK
0
Internal SCLK Mode
Internal SCLK Mode
23 22 21 20 19 18
15 14 13 12 11 10
32 clocks
32 clocks
Left Channel
Left Channel
Figure 10. CS4348 Data Format (Right Justified 16)
Figure 9. CS4346 Data Format (Right Justified 24)
9 8 7
7
6 5 4 3 2 1 0
6 5 4 3 2 1 0
Right Justified, 24-Bit Data
Data Valid on Rising Edge of SCLK
SCLK Must Have at Least 48 Cycles per LRCK Period
Right Justified, 16-Bit Data
Data Valid on Rising Edge of SCLK
SCLK Must Have at Least 32 Cycles per LRCK Period
23 22 21 20 19 18
15 14 13 12 11 10
External SCLK Mode
External SCLK Mode
Right Channel
Right Channel
9 8 7
7
6 5 4 3 2 1 0
6 5 4 3 2 1 0
CS4344/5/6/8
DS613F1