AD7628KRZ Analog Devices Inc, AD7628KRZ Datasheet - Page 6

IC DAC 8BIT DUAL W/BUFF 20-SOIC

AD7628KRZ

Manufacturer Part Number
AD7628KRZ
Description
IC DAC 8BIT DUAL W/BUFF 20-SOIC
Manufacturer
Analog Devices Inc
Datasheet

Specifications of AD7628KRZ

Settling Time
400ns
Number Of Bits
8
Number Of Converters
2
Voltage Supply Source
Single Supply
Power Dissipation (max)
450mW
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
20-SOIC (7.5mm Width)
Resolution (bits)
8bit
Input Channel Type
Parallel
Data Interface
Parallel
Supply Voltage Range - Analogue
10.8V To 15.75V
Supply Current
2mA
Digital Ic Case Style
SOIC
No. Of Pins
20
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

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Part Number:
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AD7628
APPLICATIONS INFORMATION
Application Hints
To ensure system performance consistent with AD7628 specifi-
cations, careful attention must be given to the following points:
1. GENERAL GROUND MANAGEMENT: AC or transient
2. OUTPUT AMPLIFIER OFFSET: CMOS DACs exhibit a
3. HIGH FREQUENCY CONSIDERATIONS: The output
DYNAMIC PERFORMANCE
The dynamic performance of the two DACs in the AD7628 will
depend on the gain and phase characteristics of the output am-
plifiers, together with the optimum choice of the PC board lay-
out and decoupling components. Figure 6 shows the relationship
between input frequency and channel-to-channel isolation.
Figure 7. Suggested PC Board Layout for AD7628 with
AD644 Dual Op Amp
voltages between the AD7628 AGND and DGND can cause
noise injection into the analog output. The simplest method
of ensuring that voltages at AGND and DGND are equal is
to tie AGND and DGND together at the AD7628. In more
omplex systems where the AGND–DGND intertie is on the
backplane, it is recommended that diodes be connected in
inverse parallel between the AD7628 AGND and DGND
pins (1N914 or equivalent).
code-dependent output resistance which, in turn, causes a
code-dependent amplifier noise gain. The effect is a code-
dependent differential nonlinearity term at the amplifier
output that depends on V
voltage). This differential nonlinearity term adds to the R/2R
differential nonlinearity. To maintain monotonic operation, it
is recommended that amplifier V
1 LSB over the temperature range of interest.
capacitance of a CMOS DAC works in conjunction with the
amplifier feedback resistance to add a pole to the open loop
response. This can cause ringing or oscillation. Stability can
be restored by adding a phase compensation capacitor in
parallel with the feedback resistor.
Figure 6. Channel-to-Channel Isolation
OS
(V
OS
OS
is amplifier input offset
be no greater than 10% of
–6–
Figure 7 shows a printed circuit layout for the AD7628 and the
AD644 dual op amp, which minimizes feedthrough and crosstalk.
SINGLE SUPPLY APPLICATIONS
The AD7628 DAC R-2R ladder termination resistors are con-
nected to AGND within the device. This arrangement is par-
ticularly convenient for single supply operation because AGND
may be biased at any voltage between DGND and V
8 shows a circuit that provides two +5 V to +8 V analog outputs
by biasing AGND +5 V up from DGND. The two DAC refer-
ence inputs are tied together and a reference input voltage is ob-
tained without a buffer amplifier by making use of the constant
and matched impedances of the DAC A and DAC B reference
inputs. Current flows through the two DAC R-2R ladders into
R1, and R1 is adjusted until the V
at +2 V. The two analog output voltages range from +5 V to
+8 V for DAC codes 00000000 to l l l l l l l l .
Figure 9 shows DAC A of the AD7628 connected in a positive
reference, voltage switching mode. This configuration is useful
because V
operation. However, to retain specified linearity, V
the range 0 V to +2.5 V and the output buffered or loaded with
a high impedance (see Figure 10). Note that the input voltage is
connected to the DAC OUT A, and the output voltage is taken
from the DAC V
Figure 10. Typical AD7628 Performance in Single Supply
Voltage Switching Mode
Figure 9. AD7628 Single Supply, Voltage Switching Mode
Figure 8. AD7628 Single Supply Operation
OUT
is the same polarity as V
REF
A pin.
REF
A and V
IN
, allowing single supply
REF
B inputs are
IN
DD
must be in
. Figure
REV. A

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