CS4340-CZZ Cirrus Logic Inc, CS4340-CZZ Datasheet - Page 17

• Manufacturer Part Number: CS4340-CZZ
• Description: IC DAC 24BIT 96KHZ 101DB 16TSSOP
• Manufacturer: Cirrus Logic Inc

Specifications of CS4340-CZZ

• Data Interface: Serial
• Number Of Bits: 24
• Number Of Converters: 2
• Voltage Supply Source: Single Supply
• Power Dissipation (max): 90mW
• Operating Temperature: -10°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 16-TSSOP
• Resolution (bits): 24bit
• Sampling Rate: 96kSPS
• Input Channel Type: Serial
• Supply Current: 15mA
• Digital Ic Case Style: TSSOP
• No. Of Pins: 16
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: CDB4340A - EVALUATION BOARD FOR CS4340A
• Settling Time: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 598-1049-5

4.2.2 External Serial Clock Mode
4.3
The device will accept audio samples in several digital interface formats as illustrated in Table 5. The desired format
is selected via the DIF1 and DIF0 pins. For an illustration of the required relationship between LRCK, SCLK and
SDIN, see Figures 15 through 18.
DS297F3
LR C K
S C L K
SDIN
LR C K
S C L K
SDIN
The internal serial clock is utilized when additional de-emphasis control is required. Operation in the Internal
Serial Clock mode is identical to operation with an external SCLK synchronized with LRCK; however, External
SCLK mode is recommended for system clocking applications.
The device will enter the External Serial Clock Mode whenever 16 low to high transitions are detected on the
SCLK pin during any phase of the LRCK period. The device will revert to Internal Serial Clock Mode if no low
to high transitions are detected on the SCLK pin for 2 consecutive periods of LRCK.
Digital Interface Format
512, 256, 128
512, 256, 128
MCLK/LRCK
MSB
384, 192
MSB
Ratio
Input
-1 -2 -3 -4 -5
-1 -2 -3 -4 -5
DIF1
Figure 16. CS4340 Format 1 - Left Justified up to 24-Bit Data
0
0
1
1
Figure 15. CS4340 Format 0 - I
DIF0
I
0
1
0
1
Table 5. Digital Interface Format - DIF1 and DIF0
2
+5 +4
S up to 24
Left C ha nnel
+5 +4
Left C ha nnel
Bits
X
X
I
Left Justified, up to 24-bit data
Right Justified, 24-bit Data
Right Justified, 16-bit Data
-
2
S, up to 24-bit data
+3 +2 +1
+3 +2 +1
Table 4. Internal SCLK/LRCK Ratio
LSB
Digital Interface Format Selection
Left Justified 24
LSB
DESCRIPTION
Bits
X
X
-
2
Right Justified
S up to 24-Bit Data
24 Bits
X
X
-
MSB
MSB
FORMAT
-1 -2 -3 -4
-1 -2 -3 -4
0
1
2
3
Right Justified
16 Bits
FIGURE
+5 +4
X
X
-
+5 +4
R ig ht C ha nnel
R ig ht C ha nnel
15
16
17
18
+3 +2 +1
+3 +2 +1
SCLK/LRCK
Internal
LSB
LSB
Ratio
32
48
64
CS4340
17