CS4397-KSZ Cirrus Logic Inc, CS4397-KSZ Datasheet - Page 21

• Manufacturer Part Number: CS4397-KSZ
• Description: IC DAC 24BIT MULTY STNDRD 28SOIC
• Manufacturer: Cirrus Logic Inc

Specifications of CS4397-KSZ

• Data Interface: Serial
• Number Of Bits: 24
• Number Of Converters: 2
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -10°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 28-SOIC
• Resolution (bits): 24bit
• Sampling Rate: 192kSPS
• Input Channel Type: Serial
• Supply Voltage Range - Analog: 4.75V To 5.25V
• Supply Current: 20mA
• Digital Ic Case Style: SOIC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power Dissipation (max): -
• Settling Time: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 598-1066-5

Common Mode Voltage - CMOUT
Reference Ground - FILT-
Reference Filter - FILT+
Voltage Reference Input- VREF
HARDWARE MODE
Mode Select - M0, M1, M2, M3, M4
CONTROL PORT MODE
Address Bit 0 / Chip Select - AD0 / CS
DS333F1
Pin 25, Output
Function:
Pin 26, Input
Function:
Pin 27, Output
Function:
Pin 28, Input
Function:
Pins 2, 3, 4, 5 and 14, Inputs
Function:
Pin 2, Input
Function:
Filter connection for internal bias voltage, typically 50% of VREF. Capacitors must be connected from
CMOUT to analog ground, as shown in Figure 6. CMOUT has a typical source impedence of 25 kΩ and
any current drawn from this pin will alter device performance
Ground reference for the internal sampling circuits. Must be connected to analog ground.
Positive reference for internal sampling circuits. External capacitors are required from FILT+ to analog
ground, as shown in Figure 6. The recommended values will typically provide 60 dB of PSRR at 1 kHz
and 40 dB of PSRR at 120 Hz. FILT+ is not intended to supply external current.
Analog voltage reference. Typically 5VDC.
The Mode Select pins determine the operational mode of the device as detailed in Tables 9-14. The op-
tions include;
Selection of the Digital Interface Format which determines the required relationship between the
Left/Right clock, serial clock and serial data as detailed in Figures 29-33
Selection of the standard 15 µs/50 µs digital de-emphasis filter response, Figure 28, which requires re-
configuration of the digital filter to maintain the proper filter response for 32, 44.1 or 48 kHz sample rates.
Selection of the appropriate clocking mode to match the input sample rates.
Access to the Direct Stream Digital Mode
Access to the 8x Interpolation Input Mode
In I
device will enter the SPI mode at anytime a high to low transition is detected on this pin. Once the device
has entered the SPI mode, it will remain until either the part is reset or undergoes a power-down cycle.
2
C mode, AD0 is a chip address bit. CS is used to enable the control port interface in SPI mode. The
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