MT47H128M4CF-25E:G Micron Technology Inc, MT47H128M4CF-25E:G Datasheet - Page 5

• Manufacturer Part Number: MT47H128M4CF-25E:G
• Description: IC SDRAM 512MB 800MHZ 60FBGA
• Manufacturer: Micron Technology Inc
• Series: -r

Specifications of MT47H128M4CF-25E:G

• Format - Memory: RAM
• Memory Type: DDR2 SDRAM
• Memory Size: 512M (128Mx4)
• Speed: 2.5ns
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 60-TFBGA
• Lead Free Status / Rohs Status: Compliant

List of Figures
Figure 1: 512Mb DDR2 Part Numbers .............................................................................................................. 2
Figure 2: Simplified State Diagram ................................................................................................................... 8
Figure 3: 128 Meg x 4 Functional Block Diagram ............................................................................................. 11
Figure 4: 64 Meg x 8 Functional Block Diagram .............................................................................................. 12
Figure 5: 32 Meg x 16 Functional Block Diagram ............................................................................................. 12
Figure 6: 60-Ball FBGA – x4, x8 Ball Assignments (Top View) ........................................................................... 13
Figure 7: 84-Ball FBGA – x16 Ball Assignments (Top View) .............................................................................. 14
Figure 8: 84-Ball FBGA (8mm x 12.5mm) – x16 ................................................................................................ 17
Figure 9: 60-Ball FBGA (8mm x 10mm) – x4, x8 ............................................................................................... 18
Figure 10: Example Temperature Test Point Location ..................................................................................... 21
Figure 11: Single-Ended Input Signal Levels ................................................................................................... 43
Figure 12: Differential Input Signal Levels ...................................................................................................... 44
Figure 13: Differential Output Signal Levels .................................................................................................... 46
Figure 14: Output Slew Rate Load .................................................................................................................. 47
Figure 15: Full Strength Pull-Down Characteristics ......................................................................................... 48
Figure 16: Full Strength Pull-Up Characteristics ............................................................................................. 49
Figure 17: Reduced Strength Pull-Down Characteristics ................................................................................. 50
Figure 18: Reduced Strength Pull-Up Characteristics ...................................................................................... 51
Figure 19: Input Clamp Characteristics .......................................................................................................... 52
Figure 20: Overshoot ..................................................................................................................................... 53
Figure 21: Undershoot .................................................................................................................................. 53
Figure 22: Nominal Slew Rate for
Figure 23: Tangent Line for
Figure 24: Nominal Slew Rate for
Figure 25: Tangent Line for
Figure 26: Nominal Slew Rate for
Figure 27: Tangent Line for
Figure 28: Nominal Slew Rate for
Figure 29: Tangent Line for
Figure 30: AC Input Test Signal Waveform Command/Address Balls ............................................................... 66
Figure 31: AC Input Test Signal Waveform for Data with DQS, DQS# (Differential) ........................................... 66
Figure 32: AC Input Test Signal Waveform for Data with DQS (Single-Ended) .................................................. 67
Figure 33: AC Input Test Signal Waveform (Differential) ................................................................................. 67
Figure 34: MR Definition ............................................................................................................................... 75
Figure 35: CL ................................................................................................................................................ 78
Figure 36: EMR Definition ............................................................................................................................. 79
Figure 37: READ Latency ............................................................................................................................... 82
Figure 38: WRITE Latency ............................................................................................................................. 82
Figure 39: EMR2 Definition ........................................................................................................................... 83
Figure 40: EMR3 Definition ........................................................................................................................... 84
Figure 41: DDR2 Power-Up and Initialization ................................................................................................. 85
Figure 42: Example: Meeting
Figure 43: Multibank Activate Restriction ....................................................................................................... 89
Figure 44: READ Latency ............................................................................................................................... 91
Figure 45: Consecutive READ Bursts .............................................................................................................. 92
Figure 46: Nonconsecutive READ Bursts ........................................................................................................ 93
Figure 47: READ Interrupted by READ ........................................................................................................... 94
Figure 48: READ-to-WRITE ............................................................................................................................ 94
Figure 49: READ-to-PRECHARGE – BL = 4 ...................................................................................................... 95
Figure 50: READ-to-PRECHARGE – BL = 8 ...................................................................................................... 95
PDF: 09005aef82f1e6e2
512MbDDR2.pdf - Rev. Q 10/10 EN
t
t
t
t
IS ....................................................................................................................... 58
IH ...................................................................................................................... 59
DS ...................................................................................................................... 64
DH ..................................................................................................................... 65
t
RRD (MIN) and
t
t
t
t
IS .............................................................................................................. 58
IH .............................................................................................................. 59
DS ............................................................................................................. 64
DH ............................................................................................................ 65
t
RCD (MIN) .............................................................................. 88
5
Micron Technology, Inc. reserves the right to change products or specifications without notice.
512Mb: x4, x8, x16 DDR2 SDRAM
© 2004 Micron Technology, Inc. All rights reserved.
Features