SLISCD512MM1UI-A STEC, SLISCD512MM1UI-A Datasheet
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SLISCD512MM1UI-A
Specifications of SLISCD512MM1UI-A
Related parts for SLISCD512MM1UI-A
SLISCD512MM1UI-A Summary of contents
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... Lifecycle management feature allows users to monitor the device‘s block management STEC‘s IDE Single Chip Drive™ (iSCD) is the product of choice in applications requiring high reliability and high tolerance to shock, vibration, humidity, altitude, ESD, and temperature. The rugged industrial design combined with industrial temperature (-40° ...
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SLISCDxxx(M/G)M1U(I)-y Datasheet Table of Contents General Description and Key Features ................................................................................... 1 Ordering Information: IDE Single Chip Drive ......................................................................... 1 1.0 Introduction ....................................................................................................................... 4 2.0 Product Specifications ..................................................................................................... 5 2.1 Mechanical Dimensions................................................................................................................ 5 2.1.1 IDE Single Chip Drive - Single ...
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SLISCDxxx(M/G)M1U(I)-y Datasheet 6.1 Task File Register and Byte/Word/Odd-Byte Mode Mappings ................................................... 28 6.2 Host Access Interface Modes ..................................................................................................... 28 6.3 Card Information Structure (CIS) ................................................................................................ 29 6.4 Identify Drive Parameter Information .......................................................................................... 33 7.0 Registers ..........................................................................................................................34 7.1 Configuration Registers .............................................................................................................. ...
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SLISCDxxx(M/G)M1U(I)-y Datasheet 1.0 Introduction This datasheet includes the following sections: Product Specifications covers the most referenced specifications, such as mechanical dimensions, ball assignment, signal description, and performance. Flash Management explains the flash management algorithm and features, and Life ...
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SLISCDxxx(M/G)M1U(I)-y Datasheet 2.0 Product Specifications 2.1 Mechanical Dimensions 2.1.1 IDE Single Chip Drive - Single Flash Table 1 and Figure 2 show the mechanical dimensions of the IDE Single Chip Drive - Single Flash. Table 1: Mechanical dimensions iSCD - ...
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SLISCDxxx(M/G)M1U(I)-y Datasheet 2.1.2 IDE Single Chip Drive - Stacked Flash Table 2 and Figure 3 show the mechanical dimensions of the IDE Single Chip Drive – Stacked Flash. Table 2: Mechanical dimensions iSCD – Stacked Flash Parameter Length Width Height ...
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SLISCDxxx(M/G)M1U(I)-y Datasheet 2.2 Pin Assignment Note recommended to add termination resistors on the board design, as per the recommendations in the ATA-5 specifications. Pin Signal Name Number IORDY (-WAIT) 3 -CSEL* 4 -DMACK (-REG) 5 ...
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SLISCDxxx(M/G)M1U(I)-y Datasheet 2.3 Signal Descriptions Signal Name Type BVD2 I/O (PC Card Memory Mode) -SPKR (PC Card I/O Mode) -DASP (True IDE Mode) D15-D00 I/O (PC Card Memory Mode) D15-D00 PC Card I/O Mode D15-D00 (True IDE Mode) -IOWR I ...
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SLISCDxxx(M/G)M1U(I)-y Datasheet Signal Name Type -IREQ (PC Card I/O Mode) INTRQ (True IDE Mode) A10-A0 I (PC Card Memory Mode) A10-A0 (PC Card I/O Mode) A2-A0 (True IDE Mode) -CE1, -CE2 I (PC Card Memory Mode Card Enable -CE1, -CE2 ...
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SLISCDxxx(M/G)M1U(I)-y Datasheet Signal Name Type -IOIS16 (PC Card I/O Mode) -IOCS16 (True IDE Mode) -INPACK O (PC Card Memory Mode) -INPACK (PC Card I/O Mode) Input Acknowledge DMARQ (Not used for part numbers with P) (True IDE Mode) BVD1 I/O ...
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SLISCDxxx(M/G)M1U(I)-y Datasheet 2.4 Performance Table 5: iSCD Read/Write Performance Parameter Data transfer rate to/from host Sustained read Sustained write 2.5 CHS Parameters Cylinder (C) Capacity (standard) 128MB 256MB 512MB 1GB 2GB 4GB Value 25 MBytes/s (burst MBytes/s ...
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... CE, and FCC Class B & D RoHS 2.8.1 CE and FCC Class B & D The STEC products specified in this document meet the following requirements and limits of the European Standards: Class B requirements of the following European Standard: EN 55022: 1998 – ―Information technology equipment – Radio disturbance characteristics – Limits and methods of measurement‖ ...
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... SLISCDxxx(M/G)M1U(I)-y Datasheet 2.8.2 RoHS STEC certifies that its products do not contain any of the restricted substances as stated below and are in compliance with RoHS EU directive 2002/95/EC, specifically: Mercury (Hg) Cadmium Cd) Chromium VI (Cr +6) Polybrominated biphenyl (PBB) Polybrominated biphenyl ether (PBDE) ...
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SLISCDxxx(M/G)M1U(I)-y Datasheet 3.3 Wear Leveling The SLC NAND flash devices that are being used in the IDE Single Chip Drive are guaranteed for 100,000 Write/Erase cycles per block. This means that after approximately 100,000 erase cycles, the erase block has ...
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SLISCDxxx(M/G)M1U(I)-y Datasheet usable blocks and about 160 spare blocks at the time of manufacturing. Block size is 128KB for current SLC NAND flash technology. The flash media will last as long as there are spare blocks available for replacing the ...
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... Mean Time Between Failure (MTBF) STEC estimates Mean Time Between Failure (MTBF), using a prediction methodology based on reliability data for the individual components in the IDE Single Chip Drive. Table 13 below summarizes the prediction results for the IDE Single Chip Drive, based on the following two methodologies: ...
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SLISCDxxx(M/G)M1U(I)-y Datasheet 5.0 Electrical Specifications Absolute Maximum Ratings Table 14: iSCD Absolute Maximum Ratings Parameter Voltage Storage temperature range 5.1 DC Characteristics Measurements at Recommended Operating Conditions unless otherwise specified. Symbol Parameter VIL Input LOW Voltage VIH Input HIGH Voltage ...
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SLISCDxxx(M/G)M1U(I)-y Datasheet 5.2 AC Characteristics Measurements at Recommended Operating Conditions, unless otherwise specified. 5.2.1 PC Card Memory Mode Attribute Memory Read Table 16: PC Card Memory Mode Attribute Memory Read AC Characteristics Parameter Read Cycle Time Address Access Time Card ...
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SLISCDxxx(M/G)M1U(I)-y Datasheet 5.2.2 PC Card Memory Mode Attribute Memory Write Table 17: PC Card Memory Mode Attribute Memory Write AC Characteristics Parameter Write Cycle Time Write Pulse Width Address Setup Time Address Setup Time (-WE) -CE Setup Time (-WE) Data ...
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SLISCDxxx(M/G)M1U(I)-y Datasheet 5.2.3 PC Card Memory Mode Common Memory Read Table 18: PC Card Memory Mode Common Memory Read AC Characteristics Parameter Symbol Output Enable Access Time ta(OE) (max) Output Disable Time from OE tdis(OE) (max) Address Setup tsu(A) Time ...
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SLISCDxxx(M/G)M1U(I)-y Datasheet 5.2.4 PC Card Memory Mode Common Memory Write Table 19: PC Card Memory Mode Common Memory Write AC Characteristics Parameter Symbol Data Setup before tsu WE (min) (D-WEH) Data Hold following th(D) WE (min) WE Pulse Width (min) ...
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SLISCDxxx(M/G)M1U(I)-y Datasheet 5.2.5 PC Card I/O Mode Read AC Characteristics Table 20: PC Card I/O Mode Read AC Characteristics Parameter Symbol Data Delay after td(IORD) -IORD (max) Data Hold following -IORD th(IORD) (min) -IORD Width tw(IORD) Time (min) Address Setup ...
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SLISCDxxx(M/G)M1U(I)-y Datasheet 5.2.6 PC Card I/O Mode Write AC Characteristics Table 21: PC Card I/O Mode Write AC Characteristics Parameter Symbol Data Setup before -IOWR tsu(IOWR) (min) Data Hold following -IOWR th(IOWR) (min) -IOWR Width tw(IOWR) Time (min) Address Setup ...
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SLISCDxxx(M/G)M1U(I)-y Datasheet 5.2.7 True IDE Mode Register Access Table 22: True IDE Mode Register Access AC Characteristics Parameter Symbol Mode0 Cycle time (min) t0 600 Address valid to -IORD/-IOWR t1 70 (min) setup -IORD/-IOWR pulse width 8bit t2 290 (min) ...
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SLISCDxxx(M/G)M1U(I)-y Datasheet 5.2.8 True IDE Mode PIO Access Table 23: True IDE Mode PIO Access AC Characteristics Parameter Symbol Mode0 Cycle time (min) t0 600 Address valid to -IORD/-IOWR t1 70 (min) setup -IORD/-IOWR pulse width 8bit t2 290 (min) ...
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SLISCDxxx(M/G)M1U(I)-y Datasheet Figure 10: True IDE Mode PIO Access Timing Diagram 61000-04349-113, April 2008 IDE Single Chip Drive 26 ...
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SLISCDxxx(M/G)M1U(I)-y Datasheet 5.2.9 True IDE Mode Multiword DMA Table 24: True IDE Mode Multiword DMA AC Characteristics Parameter Symbol Cycle time (min) t -IORD/-IOWR Asserted Pulse t (min) -IORD data access (max) t -IORD data hold (min) t -IORD/-IOWR data ...
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SLISCDxxx(M/G)M1U(I)-y Datasheet 6.0 Host Access Specification 6.1 Task File Register and Byte/Word/Odd-Byte Mode Mappings Please refer to the iSCD standards for complete details on: Task File Register mapping for the interface modes Byte/Word/Odd-byte mode mapping within each of ...
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SLISCDxxx(M/G)M1U(I)-y Datasheet 6.3 Card Information Structure (CIS) The iSCD uses a Card Information Structure (CIS) as summarized below: 1. 0000: Code 01, link Tuple CISTPL_DEVICE (01), length 3 (03) at offset 0 Device type is ...
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SLISCDxxx(M/G)M1U(I)-y Datasheet 8. 0032: Code 22, link Tuple CISTPL_FUNCE (22), length 3 (03) at offset 32 Vpp is not required This is a silicon device Identify Drive Model/Serial Number is guaranteed unique ...
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SLISCDxxx(M/G)M1U(I)-y Datasheet 12. 0050: Code 1B, link Tuple CISTPL_CFTABLE_ENTRY (1B), length10 (0A) at offset 50 10 (0A) at offset 50 Configuration Table Index is 01 (default) Interface ...
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SLISCDxxx(M/G)M1U(I)-y Datasheet 16. 007D: Code 1B, link Tuple CISTPL_CFTABLE_ENTRY (1B), length 15 (0F) at offset 7D Configuration Table Index is 03 (default) ...
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... Default number of sectors per track Number of sectors per iSCD (word 7 = MSW, word 8 = LSW) Reserved Serial Number in ASCII (20 characters): STEC proprietary Do not use this word. Before retirement, was buffer type Do not use this word. Before retirement, was buffer size in 512 byte increments # of ECC bytes passed on Read/Write Long commands Firmware revision in ASCII (8 characters): Rev8 ...
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SLISCDxxx(M/G)M1U(I)-y Datasheet 7.0 Registers This chapter lists the registers of the iSCD. Refer to PC Card standards for further details. 7.1 Configuration Registers In PC Card Mode, four configuration registers, as listed in Table 26, are used. Note: In True ...
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SLISCDxxx(M/G)M1U(I)-y Datasheet 7.2 Task File Registers Table 27: iSCD Task File Registers Task File Register The Data Register is a 16-bit read/write register used for transferring data Data Register between the iSCD and the host. This register can be accessed ...
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SLISCDxxx(M/G)M1U(I)-y Datasheet 8.0 Supported ATA Commands The ATA commands used by the iSCD are listed in Table 28. Refer to PC Card standards for details. Table 28: iSCD Supported ATA Commands Command Set Code Check Power Mode E5h or 98h ...
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SLISCDxxx(M/G)M1U(I)-y Datasheet Command Set Code Set Features EFh Set Multiple Mode C6h Set Sleep Mode E6h or 99h Stand By E2h or 96h Stand By Immediate E0h or 94h Translate Sector 87h Wear Level F5h Write Buffer E8h Write DMA ...
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SLISCDxxx(M/G)M1U(I)-y Datasheet 9.0 Evaluating IDE Single Chip Drive An Evaluation Board is available for customers that do not yet have the hardware layout ready for the IDE Single Chip Drive 50-ball footprint. The Evaluation Board has an IDE Single Chip ...
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... Layout updated for consistency and easier editing. Disclaimer notice reformatted with headings. -111 3/7/08 Contact information on last page updated. -112 4/2/08 STEC China address on last page updated. -113 4/8/08 Pinout 4 and 8 transposed in Pin Assignments table. 61000-04349-113, April 2008 IDE Single Chip Drive 39 ...
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... Please contact the STEC™ Inc. sales office to obtain the latest specifications. STEC™ Inc. grants no warranty with respect to this datasheet, neither explicit or implied, and is not liable for direct or indirect damages. Some states do not grant the exclusion of incidental damages and as such this statement may not be valid in such states ...