SLISCD512MM1UI-A STEC, SLISCD512MM1UI-A Datasheet - Page 10

• Manufacturer Part Number: SLISCD512MM1UI-A
• Manufacturer: STEC
• Type: Chip Driver

Specifications of SLISCD512MM1UI-A

• Density: 512MByte
• Operating Supply Voltage (typ): 3.3/5V
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Package Type: Chip
• Mounting: Surface Mount
• Pin Count: 50
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 3.18/4.75V
• Operating Supply Voltage (max): 3.465/5.25V
• Programmable: Yes
• Lead Free Status / Rohs Status: Compliant

SLISCDxxx(M/G)M1U(I)-y
Datasheet
-IOIS16
(PC Card I/O Mode)
-IOCS16
(True IDE Mode)
-INPACK
(PC Card Memory Mode)
-INPACK
(PC Card I/O Mode)
Input Acknowledge
DMARQ (Not used for part
numbers with P)
(True IDE Mode)
BVD1
(PC Card Memory Mode)
-STSCHG
(PC Card I/O Mode)
Status Changed
-PDIAG
(True IDE Mode)
-WAIT
(PC Card Memory Mode)
-WAIT
(PC Card I/O Mode)
IORDY
(True IDE Mode)
GND
(PC Card Memory Mode)
GND
(PC Card I/O Mode)
GND
(True IDE Mode)
VCC
(PC Card Memory Mode)
VCC
(PC Card I/O Mode)
VCC
(True IDE Mode)
RESET
(PC Card Memory Mode)
RESET
(PC Card I/O Mode)
-RESET
(True IDE Mode)
-VS1
-VS2
(True IDE Mode)
Signal Name
Type
GND
VCC
I/O
O
O
I
Number
61000-04349-113, April 2008
27, 28
37, 38
Pin
29
34
12
2
A low signal indicates that a 16 bit or odd byte only operation
can be performed at the addressed port.
Not defined in IDE Mode.
This signal is not used in this mode.
The Input Acknowledge signal is asserted by the iSCD when
it is selected and responding to an I/O read cycle at the
address that is on the bus. The host uses this signal to
control the enable of any input data buffers between the
iSCD and the host‘s CPU.
In True IDE Mode this signal is asserted by the iSCD when it
is ready to transfer data to/from the host. Data direction is
controlled by -IORD and -IOWR. This signal is used in a
handshake manner with -DMACK.
This signal is asserted high as since a battery is not used
with this product.
This signal is asserted low to alert the host to changes in the
RDY/-BSY and Write Protect states. Its use is controlled by
the Configuration and Status Register.
In True IDE Mode, this input/output signal is the Pass
Diagnostic signal in the Master/Slave handshake protocol.
This signal is not used by the iSCD, and is pulled up to VCC
through a 4.7K ohm resistor.
This signal is not used by the iSCD, and is pulled up to VCC
through a 4.7K ohm resistor.
This signal is not used by the iSCD, and is pulled up to VCC
through a 4.7K ohm resistor.
Ground
Ground
Ground
+5 V or 3.3V power
+5 V or 3.3V power
+5 V or 3.3V power
When RESET is high, this signal resets the iSCD. The iSCD is
reset only at power up if this signal is left high or open from power-
up. The iSCD can also be reset when the soft reset bit in the
Configuration Option Register is set.
This signal is the same as the PC Card Memory Mode signal.
In the True IDE Mode this input pin is the active low hardware
reset from the host.
This signal is not used in IDE Mode.
Description
IDE Single Chip Drive
10