CY8C5246AXI-054 Cypress Semiconductor Corp, CY8C5246AXI-054 Datasheet
CY8C5246AXI-054
Specifications of CY8C5246AXI-054
Related parts for CY8C5246AXI-054
CY8C5246AXI-054 Summary of contents
Page 1
... Full-Speed (FS) USB 2.0 12 Mbps using internal oscillator Four 16-bit configurable timer, counter, and PWM blocks Library of standard peripherals Note 1. This feature on select devices only. See Ordering Information Cypress Semiconductor Corporation Document Number: 001-55034 Rev. *F PRELIMINARY ® PSoC 5: CY8C52 Family Data Sheet Programmable System-on-Chip (PSoC ® ...
Page 2
Content Overview 1. ARCHITECTURAL OVERVIEW ......................................... 3 2. PINOUTS ............................................................................. 5 3. PIN DESCRIPTIONS ........................................................... 9 4. CPU ................................................................................... 10 4.1 ARM Cortex-M3 CPU ............................................... 10 4.2 Cache Controller ...................................................... 12 4.3 DMA and PHUB ....................................................... 12 4.4 Interrupt Controller ...
Page 3
Architectural Overview Introducing the CY8C52 family of ultra low power, flash Programmable System-on-Chip (PSoC ® PSoC 3 and 32-bit PSoC 5 platform. The CY8C52 family provides configurable blocks of analog, digital, and interconnect circuitry around a CPU subsystem. The ...
Page 4
Figure 1-1 illustrates the major components of the CY8C52 family. They are: ARM Cortex-M3 CPU Subsystem Nonvolatile Subsystem Programming, Debug, and Test Subsystem Inputs and Outputs Clocking Power Digital Subsystem Analog Subsystem PSoC’s digital subsystem provides half of its unique ...
Page 5
The device provides a PLL to generate system clock frequencies MHz from the IMO, external crystal, or external reference clock. It also contains a ...
Page 6
GPIO) P2[6] (TRACEDATA[3], GPIO) P2[7] (I2C0: SCL, SIO) P12[4] (I2C0: SDA, SIO) P12[5] Vboost XRES (TMS, SWDIO, GPIO) P1[0] (TCK, SWDCK, GPIO) P1[1] (configurable XRES, GPIO) P1[2] (TDO, SWV, GPIO) P1[3] (TDI, GPIO) P1[4] (nTRST, GPIO) P1[5] Vddio1 Notes ...
Page 7
GPIO) P2[5] 1 (TRACEDATA[2], GPIO) P2[6] 2 (TRACEDATA[3], GPIO) P2[7] 3 (I2C0: SCL, SIO) P12[4] 4 (I2C0: SDA, SIO) P12[5] 5 (GPIO) P6[4] 6 (GPIO) P6[5] 7 (GPIO) P6[6] 8 (GPIO) P6[7] 9 Vssb 10 Ind 11 Vboost 12 ...
Page 8
Figure 2-3 and Figure 2-4 show an example schematic and an example PCB layout, for the 100-pin TQFP part, for optimal analog performance on a 2-layer board. The two pins labeled Vddd must be connected together. The two pins labeled ...
Page 9
Figure 2-4. Example PCB Layout for 100-Pin TQFP Part for Optimal Analog Performance Vssd Plane 3. Pin Descriptions IDAC0. Low resistance output pin for high current DAC (IDAC). Extref0, Extref1. External reference input to the analog system. GPIO. General purpose ...
Page 10
Vdda. Supply for all analog peripherals and analog core regulator. Vdda must be the highest voltage present on the device. All other supply pins must be less than or equal to Vdda. Vddd. Supply for all digital peripherals and digital ...
Page 11
External Memory Interface (EMIF) 4.1.1 Cortex-M3 Features The Cortex-M3 CPU features include address space. Predefined address regions for code, data, and peripherals. Multiple buses for efficient and simulta- neous accesses of instructions, data, and peripherals. ® The Thumb ...
Page 12
Table 4-2. Cortex M3 CPU Registers (continued) Register Description BASEPRI A register nine bits that define the masking priority level. When set, it disables all interrupts of the same or higher priority value. If set to 0 ...
Page 13
Table 4-4. Priority Levels Priority Level % Bus Bandwidth 0 100.0 1 100.0 2 50.0 3 25.0 4 12.5 5 6.2 6 3.1 7 1.5 4.3.4 Transaction Modes Supported The flexible configuration of each DMA channel and the ability to ...
Page 14
Interrupt Controller The Cortex-M3 NVIC supports 16 system exceptions and 32 interrupts from peripherals, as shown in Table Table 4-5. Cortex-M3 Exceptions and Interrupts Exception Exception Type Number 1 Reset -3 (highest) 2 NMI -2 3 Hard fault -1 ...
Page 15
Table 4-6. Interrupt Vector Table (continued) Interrupt # Cortex-M3 Exception # ...
Page 16
PSoC Creator, for example). If your application requires code update through a boot loader, then use the Field Upgrade setting. Use the Unprotected setting only when no security is needed in your application. The PSoC device also ...
Page 17
Data, Address, and Control Signals PHUB Data, Address, and Control Signals Data, Address, and Control Signals Document Number: 001-55034 Rev. *F PRELIMINARY ® PSoC Figure 5-1. EMIF Block Diagram Address Signals PORTs Data Signals IO IF PORTs Control Signals PORTs ...
Page 18
Memory Map The Cortex-M3 has a fixed address map, which allows periph- erals to be accessed by simple memory access instructions. 5.6.1 Address Map The 4 GB address space is divided into the ranges shown in Table 5-2: Table ...
Page 19
System Integration 6.1 Clocking System The clocking system generates, divides, and distributes clocks throughout the PSoC system. For the majority of systems, no external crystal is required. The IMO and PLL together can generate MHz ...
Page 20
MHz 4-33 MHz IMO ECO 12-48 MHz Doubler Digital Clock Divider 16 bit Digital Clock Divider 16 bit 7 Digital Clock Divider 16 bit Digital Clock Divider 16 bit 6.1.1 Internal Oscillators 6.1.1.1 Internal Main Oscillator In most designs ...
Page 21
It can be used to generate periodic inter- rupts for timing purposes or to wake the system from a low power mode. Firmware can reset the central timewheel. The central timewheel can be programmed to wake ...
Page 22
Clock Distribution All seven clock sources are inputs to the central clock distribution system. The distribution system is designed to create multiple high precision clocks. These clocks are customized for the design’s requirements and eliminate the common problems found ...
Page 23
Power System The power system consists of separate analog, digital, and I/O supply pins, labeled V includes two internal 1.8 V regulators that provide the digital (Vccd) and analog (Vcca) supplies for the internal core logic. The output pins ...
Page 24
Table 6-2. Power Modes Power Modes Description Active Primary mode of operation, all peripherals available (program- mable) Alternate Similar to Active mode, and is Active typically configured to have fewer peripherals active to reduce power. One possible configuration is to ...
Page 25
Alternate Active Mode Alternate Active mode is very similar to Active mode. In alternate active mode, fewer subsystems are enabled, to reduce power consumption. One possible configuration is to turn off the CPU and flash, and run peripherals at ...
Page 26
Reset CY8C52 has multiple internal and external reset sources available. The reset sources are: Power source monitoring - The analog and digital power voltages Vcca, and Vccd are monitored in several DDA DDD different modes ...
Page 27
The external reset is active low. It includes an internal pull up resistor. XRES is active during sleep and hibernate modes. SRES - Software Reset A reset can be commanded under program control by setting a bit in the software ...
Page 28
Digital Input Path PRT[x]CTL PRT[x]DBL_SYNC_IN PRT[x]PS Digital System Input PICU[x]INTTYPE[y] PICU[x]INTSTAT Pin Interrupt Signal PICU[x]INTSTAT Digital Output Path PRT[x]SLW PRT[x]SYNC_OUT PRT[x]DR Digital System Output PRT[x]BYP PRT[x]DM2 PRT[x]DM1 PRT[x]DM0 Bidirectional Control PRT[x]BIE Analog Capsense Global Control CAPS[x]CFG1 PRT[x]AG Analog Global Enable ...
Page 29
Digital Input Path PRT[x]SIO_HYST_EN PRT[x]SIO_DIFF Reference Level PRT[x]DBL_SYNC_IN PRT[x]PS Digital System Input PICU[x]INTTYPE[y] PICU[x]INTSTAT Pin Interrupt Signal PICU[x]INTSTAT Digital Output Path Reference Level PRT[x]SIO_CFG PRT[x]SLW PRT[x]SYNC_OUT PRT[x]DR Digital System Output PRT[x]BYP PRT[x]DM2 PRT[x]DM1 PRT[x]DM0 Bidirectional Control PRT[x]BIE Digital Input Path ...
Page 30
Drive Modes Each GPIO and SIO pin is individually configurable into one of the eight drive modes listed in Table 6-6. Three configuration bits are used for each pin (DM[2:0]) and set in the PRTxDM[2:0] registers. Figure 6-11 depicts ...
Page 31
Pins can be used for digital input and output in these modes. Interfacing to mechanical switches is a common appli- cation for these modes. Open Drain, Drives High and Open Drain, Drives Low Open drain modes provide high impedance ...
Page 32
Typically the voltage DAC (VDAC) is used to generate the reference. The page 51 has more details on VDAC use and reference routing to the SIO pins. 6.4.12 Adjustable Input Level This section applies ...
Page 33
Digital Subsystem The digital programmable system creates application specific combinations of both standard and advanced digital peripherals and custom logic functions. These peripherals and logic are then interconnected to each other and to any pin on the device, providing ...
Page 34
Example Digital Components The following is a sample of the digital components available in PSoC Creator for the CY8C52 family. The exact amount of hardware resources (UDBs, routing, RAM, flash) used by a component varies with the features selected ...
Page 35
PSoC Creator automatically configures clocks and routes the I/O to the selected pins and then generates APIs to give the appli- cation complete control over the hardware. Changing the PSoC device configuration is as simple as adding a new component, ...
Page 36
Component Catalog Figure 7-3. Component Catalog The component catalog is a repository of reusable design elements that select device functionality and customize your PSoC device populated with an impressive selection of content; from simple primitives such as ...
Page 37
PSoC Creator contains all the tools necessary to complete a design, and then to maintain and extend that design for years to come. All steps of the design flow are carefully integrated and optimized for ease-of-use and to maximize productivity. ...
Page 38
Datapath Module The datapath contains an 8-bit single cycle ALU, with associated compare and condition generation logic. This datapath block is Input Muxes Input from Programmable Routing 6 PI Parallel Input/Output (to/from Programmable Routing) PO 7.2.2.6 Working Registers The ...
Page 39
Logical OR Logical XOR Pass, used to pass a value through the ALU to the shift register, mask, or another UDB register Independent of the ALU operation, these functions are available: Shift left Shift right Nibble swap Bitwise OR mask ...
Page 40
Status and Control Module The primary purpose of this circuitry is to coordinate CPU firmware interaction with internal UDB operation. Figure 7-10. Status and Control Registers System Bus 8-bit Status Register 8-bit Control Register (Read Only) (Write/Read) Routing Channel ...
Page 41
Figure 7-12. Function Mapping Example in a Bank of UDBs 8-Bit 16-Bit Quadrature Decoder Timer PWM UDB UDB UDB UDB UDB UDB 8-Bit SPI I2C Slave 12-Bit SPI UDB UDB UDB Logic ...
Page 42
I/O Port Routing There are a total of 20 DSI routes to a typical 8-bit I/O port, 16 for data and four for drive strength control. When an I/O pin is connected to the routing, there are two primary ...
Page 43
CAN Node 1 PSoC CAN Drivers CAN Controller CAN Transceiver CAN_H CAN_L 7.5.1 CAN Features CAN2.0A/B protocol implementation - ISO 11898 compliant Standard and extended frames with bytes of data per frame Message filter ...
Page 44
Tx Buffer Status TxReq Pending TxInterrupt Request (if enabled) RxMessage0 Acceptance Code 0 Rx Buffer Status RxMessage RxMessage1 Acceptance Code 1 Available RxMessage14 Acceptance Code 14 RxInterrupt RxMessage15 Acceptance Code 15 Request (if enabled) 7.6 USB PSoC includes a dedicated ...
Page 45
Timers, Counters, and PWMs The Timer/Counter/PWM peripheral is a 16-bit dedicated peripheral providing three of the most common embedded peripheral features. As almost all embedded systems use some combination of timers, counters, and PWMs. Four of them have been ...
Page 46
GPIO Port DSI Array The PSoC Creator software program provides a user friendly interface to configure the analog connections between the GPIO and various analog resources and ...
Page 47
ExVrefL ExVrefL1 GPIO P0[4] GPIO P0[5] GPIO * i0 P0[6] GPIO * P0[7] cmp0_vref (1.024V) GPIO cmp_muxvn[1:0] vref_cmp1 P4[2] cmp1_vref (0.256V) bg_vda_res_en GPIO Vdda Vdda/2 P4[3] refbuf_vref1 (1.024V) refbuf_vref2 (1.2V) GPIO P4[4] refsel[1:0] GPIO vssa P4[5] ...
Page 48
Analog local buses (abus) are routing resources located within the analog subsystem and are used to route signals between different analog blocks. There are eight abus routes in CY8C38, four in the left half (abusl [0:3]) and four in the ...
Page 49
From Analog Routing 8.3.2 LUT The CY8C52 family of devices contains two LUTs. The LUT is a two input, one output lookup table that is driven by one or two of the comparators in the chip. The output of any ...
Page 50
LCD Direct Drive The PSoC Liquid Crystal Display (LCD) driver system is a highly configurable peripheral designed to allow PSoC to directly drive a broad range of LCD glass. All voltages are generated on chip, eliminating the need for ...
Page 51
CapSense The CapSense system provides a versatile and efficient means for measuring capacitance in applications such as touch sense buttons, sliders, proximity detection, etc. The CapSense system uses a configuration of system resources, including a few hardware functions primarily ...
Page 52
Programming, Debug Interfaces, Resources The Cortex-M3 has internal debugging components, tightly integrated with the CPU, providing the following features: JTAG or SWD access Flash Patch and Breakpoint (FPB) block for implementing breakpoints and code patches Data Watchpoint and Trigger ...
Page 53
Trace Features The following trace features are supported: Instruction trace Data watchpoint on access to data address, address range, or data value Trace trigger on data watchpoint Debug exception trigger Code profiling Counters for measuring clock cycles, folded instructions, ...
Page 54
Development Support The CY8C52 family has a rich set of documentation, devel- opment tools, and online resources to assist you during your development process. Visit psoc.cypress.com/getting-started find out more. 10.1 Documentation A suite of documentation, to ensure that you ...
Page 55
Electrical Specifications Specifications are valid for -40°C ≤ T ≤ 85°C and T A where noted. The unique flexibility of the PSoC UDBs and analog blocks enable many functions to be implemented in PSoC Creator components, see the component ...
Page 56
Device Level Specifications Specifications are valid for -40°C ≤ T ≤ 85°C and T A where noted. 11.2.1 Device Level Specifications Table 11-2. DC Specifications Parameter Description V Analog supply voltage and input to DDA analog core regulator V ...
Page 57
Table 11-3. AC Specifications Parameter Description F CPU frequency CPU F Bus frequency busclk Svdd Vdd ramp rate /Vccd/Vcca ≥ Tio_init Time from V /V DDD DDA IPOR to I/O ports set to their reset states /Vccd/Vcca ≥ Tstartup ...
Page 58
Power Regulators Specifications are valid for -40°C ≤ T ≤ 85°C and T A where noted. 11.3.1 Digital Core Regulator Table 11-4. Digital Core Regulator DC Specifications Parameter Description V Input voltage DDD Vccd Output voltage Regulator output capacitor ...
Page 59
Table 11-6. Inductive Boost Regulator DC Specifications (continued) Parameter Description [9] Boost output voltage range 1.8 V 1.9 V 2.0 V 2.4 V Vboost 2.7 V 3.0 V 3.3 V 3.6 V 5.0 V Load regulation Line regulation Efficiency Table ...
Page 60
Inputs and Outputs Specifications are valid for -40°C ≤ T ≤ 85°C and T A where noted. 11.4.1 GPIO Table 11-8. GPIO DC Specifications Parameter Description Vih Input voltage high threshold Vil Input voltage low threshold Vih Input voltage ...
Page 61
SIO Table 11-10. SIO DC Specifications Parameter Description Vinref Input voltage reference (Differential input mode) Output voltage reference (Regulated output mode) Voutref Input voltage high threshold Vih GPIO mode Differential input mode Input voltage low threshold Vil GPIO mode ...
Page 62
Table 11-11. SIO AC Specifications (continued) Parameter Description SIO output operating frequency 3.3 V < Vddio < 5.5 V, Unregulated output (GPIO) mode, fast strong drive mode 1.71 V < Vddio < 3.3 V, Unregulated output (GPIO) mode, fast strong ...
Page 63
Table 11-13. USBIO AC Specifications Parameter Description Tdrate Full-speed data rate average bit rate Tjr1 Receiver data jitter tolerance to next transition Tjr2 Receiver data jitter tolerance to pair transition Tdj1 Driver differential jitter to next transition Tdj2 Driver differential ...
Page 64
Analog Peripherals Specifications are valid for -40°C ≤ T ≤ 85°C and T A where noted. 11.5.1 Voltage Reference Table 11-17. Voltage Reference Specifications Parameter Description Vref Precision reference voltage [9] Temperature drift Long term drift Thermal cycling drift ...
Page 65
Analog Globals Table 11-20. Analog Globals AC Specifications Parameter Description Rppag Resistance pin-to-pin through [12] analog global Rppmuxbus Resistance pin-to-pin through [12] analog mux bus BWag 3 dB bandwidth of analog globals CMRRag Common mode rejection for differential signals ...
Page 66
VDAC Table 11-23. VDAC (Voltage Digital-to-Analog Converter) DC Specifications Parameter Description Resolution [9] Output resistance Rout High Low [9] Output voltage range Vout High Low INL Integral non linearity DNL Differential non linearity Ezs Zero scale error Eg Gain ...
Page 67
LCD Direct Drive Table 11-26. LCD Direct Drive DC Specifications Parameter Description Icc LCD operating current V LCD bias range (Vbias refers to the bias main output voltage(V0) of LCD DAC) LCD bias step size LCD capacitance per segment/common ...
Page 68
Digital Peripherals Specifications are valid for -40°C ≤ T ≤ 85°C and T A where noted. 11.6.1 Timer Table 11-28. Timer DC Specifications Parameter Description Block current consumption 3 MHz 12 MHz 40 MHz Table 11-29. Timer AC Specifications ...
Page 69
Pulse Width Modulation Table 11-32. PWM DC Specifications Parameter Description Block current consumption 3 MHz 12 MHz 40 MHz Table 11-33. PWM AC Specifications Parameter Description Operating frequency Pulse width Pulse width (external) Kill pulse width Kill pulse width ...
Page 70
USB Table 11-38. USB DC Specifications Parameter Description Operating current 11.6.7 Universal Digital Blocks (UDBs) PSoC Creator provides a library of pre-built and tested standard digital peripherals (UART, SPI, LIN, PRS, CRC, timer, counter, PWM, AND, OR, and so ...
Page 71
Memory Specifications are valid for -40°C ≤ T ≤ 85°C and T A where noted. 11.7.1 Flash Table 11-40. Flash DC Specifications Parameter Description Erase and program voltage Table 11-41. Flash AC Specifications Parameter Description Twrite Row write time ...
Page 72
Table 11-45. NVL AC Specifications Parameter Description NVL endurance NVL data retention time 11.7.4 SRAM Table 11-46. SRAM DC Specifications Parameter Description Vsram SRAM retention voltage Table 11-47. SRAM AC Specifications Parameter Description Fsram SRAM operating frequency 11.7.5 External Memory ...
Page 73
Table 11-48. Asynchronous Read Cycle Specifications (continued) Parameter Description Toel EM_OEn low time Toeh EM_OEn high to EM_CEn high hold time Tdoesu Data to EM_OEn high setup time Tdcesu Data to EM_CEn high setup time Tdoeh Data hold time after ...
Page 74
Tcp EM_ Clock Tceld EM_ CEn Taddrv EM_ Addr Toeld EM_ OEn EM_ Data Tadscld EM_ ADSCn Table 11-50. Synchronous Read Cycle Specifications Parameter Description T EMIF Clock period Tcp EM_Clock Period Tceld EM_Clock low to EM_CEn low Tcehd EM_Clock ...
Page 75
Tcp EM_ Clock Tceld EM_ CEn Taddrv EM_ Addr Tweld EM_ WEn Tds EM_ Data Tadscld EM_ ADSCn Table 11-51. Synchronous Write Cycle Specifications Parameter Description T EMIF Clock period Tcp EM_Clock Period Tceld EM_Clock low to EM_CEn low Tcehd ...
Page 76
PSoC System Resources Specifications are valid for -40°C ≤ T ≤ 85°C and T A where noted. 11.8.1 POR with Brown Out For brown out detect in regulated mode, V Table 11-52. Precise Power On Reset (PRES) with Brown ...
Page 77
Interrupt Controller Table 11-56. Interrupt Controller AC Specifications Parameter Description Delay from Interrupt signal input to ISR code execution from main line code Delay from Interrupt signal input to ISR code execution from ISR code 11.8.4 JTAG Interface Table ...
Page 78
Clocking Specifications are valid for -40°C ≤ T ≤ 85°C and T A where noted. 11.9.1 32 kHz External Crystal Table 11-60. 32 kHz External Crystal DC Specifications Parameter Description Icc Operating current CL External crystal capacitance DL Drive ...
Page 79
Internal Low Speed Oscillator Table 11-64. ILO DC Specifications Parameter Description Operating current Icc Leakage current Table 11-65. ILO AC Specifications Parameter Description Startup time Startup time Startup time Duty cycle ILO frequencies (trimmed) 100 kHz 1 kHz Filo ...
Page 80
Phase-Locked Loop Table 11-68. PLL DC Specifications Parameter Description Idd PLL operating current Table 11-69. PLL AC Specifications Parameter Description [18] Fpllin PLL input frequency PLL intermediate frequency [18] Fpllout PLL output frequency Lock time at startup [9] Jperiod-rms ...
Page 81
... Table 12-1. CY8C52 Family with ARM Cortex-M3 CPU MCU Core Part Number 64 KB Flash ✔ 1x12-bit SAR 1 CY8C5246AXI-038 ✔ 1x12-bit SAR 1 CY8C5246LTI-087 ✔ 1x12-bit SAR 1 CY8C5246AXI-054 ✔ 1x12-bit SAR 1 CY8C5246LTI-029 ✔ 1x12-bit SAR 1 CY8C5246AXI-093 ✔ 1x12-bit SAR 1 CY8C5246AXI-002 128 KB Flash ✔ ...
Page 82
Part Numbering Conventions PSoC 5 devices follow the part numbering convention described below. All fields are single character alphanumeric ( … …, Z) unless stated otherwise. CY8Cabcdefg-xxx a: Architecture 3: PSoC 3 5: PSoC ...
Page 83
Packaging Table 13-1. Package Characteristics Parameter Description T Operating ambient temperature A T Operating junction temperature J Package θ JA (68 QFN) Tja Package θ JA (100 TQFP) Tja Package θ JC (68 QFN) Tjc Package θ JC (100 ...
Page 84
Figure 13-2. 100-Pin TQFP ( 1.4 mm) Package Outline 16.00±0.25 SQ 14.00±0.05 SQ 100 SEATING PLANE 1.60 MAX. 0.08 0.20 MAX. Document Number: 001-55034 Rev. *F PRELIMINARY ® PSoC 5: CY8C52 Family Data Sheet ...
Page 85
Revision History ® Description Title: PSoC 5: CY8C52 Family Data Sheet Programmable System-on-Chip (PSoC Document Number: 001-55034 Submission Rev. ECN No. Date ** 2759055 09/02/09 *A 2824626 12/09/09 *B 2873520 02/04/10 Document Number: 001-55034 Rev. *F PRELIMINARY ® PSoC ...
Page 86
Description Title: PSoC 5: CY8C52 Family Data Sheet Programmable System-on-Chip (PSoC Document Number: 001-55034 *C 2911720 04/13/10 Document Number: 001-55034 Rev. *F PRELIMINARY ® PSoC 5: CY8C52 Family Data Sheet MKEA Updated Vb pin in PCB Schematic. Updated Tstartup ...
Page 87
Description Title: PSoC 5: CY8C52 Family Data Sheet Programmable System-on-Chip (PSoC Document Number: 001-55034 *D 2936486 05/24/10 *E 2944841 6/4/2010 *F 2960407 06/24/10 Document Number: 001-55034 Rev. *F PRELIMINARY ® PSoC 5: CY8C52 Family Data Sheet MKEA Replaced Vddio ...
Page 88
... Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement ...