CY8C5246AXI-054 Cypress Semiconductor Corp, CY8C5246AXI-054 Datasheet - Page 80

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CY8C5246AXI-054

Manufacturer Part Number
CY8C5246AXI-054
Description
Manufacturer
Cypress Semiconductor Corp
Datasheets

Specifications of CY8C5246AXI-054

Lead Free Status / Rohs Status
Compliant
11.9.6 Phase-Locked Loop
Table 11-68. PLL DC Specifications
Table 11-69. PLL AC Specifications
Document Number: 001-55034 Rev. *F
Idd
Fpllin
Fpllout
Jperiod-rms Jitter (rms)
Notes
Parameter
Parameter
18. This specification is guaranteed by testing the PLL across the specified range using the IMO as the source for the PLL.
19. PLL input divider, Q, must be set so that the input frequency is divided down to the intermediate frequency range. Value for Q ranges from 1 to 16.
PLL operating current
PLL input frequency
PLL intermediate frequency
PLL output frequency
Lock time at startup
PLL output duty cycle
[9]
Description
Description
[18]
[18]
[19]
PRELIMINARY
In = 3 MHz, Out = 24 MHz
Output of prescaler
All PLL output frequencies
Conditions
Conditions
PSoC
®
5: CY8C52 Family Data Sheet
Min
Min
24
45
1
1
-
-
-
Typ
200
Typ
-
-
-
-
-
-
Max
Max
250
250
48
67
55
3
-
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Units
Units
MHz
MHz
MHz
µA
µs
ps
%
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