NH82801FB S L89L Intel, NH82801FB S L89L Datasheet - Page 17

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NH82801FB S L89L

Manufacturer Part Number
NH82801FB S L89L
Description
Manufacturer
Intel
Datasheet

Specifications of NH82801FB S L89L

Mounting
Surface Mount
Lead Free Status / Rohs Status
Compliant
17.
Problem:
Implication:
Workaround:
Status:
18.
Problem:
Implication:
Workaround:
Status:
19.
Problem:
Implication:
Workaround:
Status:
20.
Problem:
Implication:
Workaround:
Status:
Intel® ICH6 Family Specification Update
Intel
In only AHCI mode (ICH6R), the SATA controller may post a FIS incorrectly if either an
unsolicited COMINIT arrives or if software performs a port reset, while FIS posting is pending
internally.
Both a malformed TLP is delivered and inappropriate data is delivered on the next upstream cycle.
None. The system can be configured to detect this anomalous condition and reset the system to
prevent this data migration. Refer to the ICH6 BIOS Specification for implementation details.
No Fix. For steppings affected, see the Summary Tables of Changes.
USB Output Voltage
ICH6 High Speed USB2.0 V
None known.
None.
No Fix. For steppings affected, see the Summary Tables of Changes.
Intel
If the ICH6 SATA controller is operating in AHCI mode and a device sends a SYNC escape, the
ICH6 retries the Command FIS (CFIS) sent to the device. The SATA spec requires that the ICH6
not resend the CFIS.
The ICH6 may continuously retry until reset by software.
None.
No Fix. For steppings affected, see the Summary Tables of Changes.
Intel
If a Task File fatal error occurs during a SATA AHCI transfer, the ICH6 will not automatically
clear the PxCMD.CR bit, as required by the AHCI 1.0 spec, until the AHCI driver software follows
the spec-defined recovery mechanism.
None known, as AHCI compliant driver software will cause the ICH6 to clear the CR bit during
error recovery.
None.
No Fix. For steppings affected, see the Summary Tables of Changes.
Note: This has only been replicated in a synthetic test environment and has not been
reproduced in a real world environment.
The maximum expected V
®
®
®
ICH6R SATA FIS Posting Cycle
ICH6 AHCI Command FIS SYNC Escape
ICH6 AHCI PxCMD.CR Bit
HSOL
HSOL
and V
is 60 mV and the maximum expected V
HSOH
may not meet the USB 2.0 specification.
HSOH
is 470 mV.
17

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