NH82801FB S L89L Intel, NH82801FB S L89L Datasheet - Page 18

• Manufacturer Part Number: NH82801FB S L89L
• Manufacturer: Intel

Specifications of NH82801FB S L89L

• Mounting: Surface Mount
• Lead Free Status / Rohs Status: Compliant

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Intel
The ICH6 High Definition Audio controller does not implement the OUTSTRMPAY and
INSTRMPAY registers, per HD Audio spec rev 1.0.
None - the ICH6 supports all standard audio useage models. Additionally, HD Audio codecs do not
support configurations that exceed the stream BW of the ICH6. However, if software programs the
audio stream to a non-standard audio format that exceeds the bandwidth capabilities of the ICH6,
then the stream’s DMA engine may halt.
None.
No Fix. For steppings affected, see the Summary Tables of Changes.
Intel
The ICH6 SATA AHCI controller may set the ERR.T and PxIS.IFS bits when a link error (such as
a CRC error) or ICH6 SATA receiver error occurs on a PIO Setup FIS, instead of setting the
PxIS.INFS bit, as defined by the AHCI 1.0 specification.
A spurious interrupt is generated and the AHCI driver software will detect the error and retry.
None.
No Fix. For steppings affected, see the Summary Tables of Changes.
Intel
After eight surprise removal or non-software initiated link down events on a PCI Express port
without a platform reset, the ICH6 may not be able to receive completions from the device on the
PCI Express link.
System may hang.
Perform platform reset.
No Fix. For steppings affected, see the Summary Tables of Changes.
PCI Express Scrambling
While entering the Recovery state, the ICH6 stops scrambling two symbols before the first TS
(training sequence).
When these non-scrambled symbols are received by the endpoint, the de-scrambler of the endpoint
will observe two symbols of random data. The first symbol of TS1 will reset the endpoint’s
de-scrambler so that the endpoint should recognize the TS1 and TS2 ordered-sets being transmitted
and move into the Recovery state as planned.
None.
No Fix. For steppings affected, see the Summary Tables of Changes.
Note: Issue requires multiple PCI Express devices to be populated in the system with
simultaneous upstream requests. Software must also deprogram the PCI Express port number
that experienced the event before hardware is able to fully respond to the link down condition.
Known software does not deprogram surprise removal port before hardware responds. This
issue has only been observed in a simulation environment.
There is no system level impact if the endpoint is PCI Express Specification 1.0a compliant in
ignoring the random data.
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ICH6 High Definition Audio Payload Capabilities Registers
ICH6 PIO Setup FIS Error
ICH6 PCI Express* Surprise Removal
Intel® ICH6 Family Specification Update