ICS87158AF IDT, Integrated Device Technology Inc, ICS87158AF Datasheet - Page 8

• Manufacturer Part Number: ICS87158AF
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of ICS87158AF

• Function: Clock Generator
• Operating Temperature (max): 85C
• Operating Temperature (min): 0C
• Package Type: SSOP
• Pin Count: 48
• Mounting: Surface Mount
• Lead Free Status / Rohs Status: Not Compliant

W
Figure 1 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = V
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio
87158AG
R
I
PCLK/nPCLK I
For applications not requiring the use of a differential input,
both the PCLK and nPCLK pins can be left floating. Though
not required, but for additional protection, a 1k
be tied from PCLK to ground.
LVCMOS C
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1k
NPUTS
ECOMMENDATIONS FOR
IRING THE
:
ONTROL
D
NPUT
IFFERENTIAL
resistor can be used.
P
:
INS
:
U
NUSED
I
F
NPUT TO
IGURE
Single Ended Clock Input
I
1. S
NPUT AND
A
A
PPLICATION
CCEPT
INGLE
resistor can
C1
0.1u
E
O
S
NDED
V_REF
UTPUT
INGLE
DD
www.idt.com
/2 is
S
IGNAL
P
E
8
INS
I
NDED
NFORMATION
O
LVCMOS O
All unused LVCMOS outputs can be left floating. There should
be no trace attached.
HCSL O
All unused HCSL outputs can be left floating. We recommend
that there is no trace attached. Both sides of the differential
output pair should either be left floating or terminated.
of R1 and R2 might need to be adjusted to position the V_REF in
the center of the input voltage swing. For example, if the input
clock swing is only 2.5V and V
and R2/R1 = 0.609.
1K
R1
1K
R2
D
UTPUTS
RIVING
VDD
1-
L
EVELS
TO
UTPUT
nPCLK
PCLK
:
D
-6, LVPECL-
UTPUT
IFFERENTIAL
:
÷1, ÷2, ÷4 C
I
NPUT
DD
= 3.3V, V_REF should be 1.25V
TO
-HCSL/LVCMOS
LOCK
ICS87158
G
REV. C JULY 25, 2010
ENERATOR