FW82546GB S L75S Intel, FW82546GB S L75S Datasheet - Page 26

• Manufacturer Part Number: FW82546GB S L75S
• Manufacturer: Intel

Specifications of FW82546GB S L75S

• Operating Supply Voltage (typ): 1.5/2.5/3.3V
• Operating Supply Voltage (min): 1.43/2.38/3V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 364
• Lead Free Status / Rohs Status: Not Compliant

82546GB — Networking Silicon
4.2
4.2.1
4.2.2
20
Pins not included in XOR test tree:
Tristate Mode
The 82546GB's tristate test mode is used to explicitly disable output drivers and place outputs in
high-impedance (tristate) state. To more readily support XOR or NAND-tree like testing of other
system components, the 82546GB decodes this test mode from the same signal pins used to
exercise XOR tree testing. The 82546GB additionally supports a mechanism to enter tristate mode
via the IEEE 802.3 JTAG (TAP) controller.
Tristate Mode Control and Operation
The following signals are required to place the 82546GB in tristate test mode:
When in tristate test mode:
Tristate Mode Using JTAG (TAP)
The 82546GB can also be placed in tristate mode using the JTAG interface and the HIGHZ
instruction.
The HIGHZ instruction is used to place the 82546GB in high-impedance (TRISTATE) mode,
where all digital signal outputs are placed in high-impedance (tri-state) output state.
Function/
Tristate
Mode
•
•
•
•
•
•
•
•
•
•
Mode
Test
JTAG (TAP) interface: TRST_N, TCK, TDO, TMS, and TDO
Test mode decode controls TEST_DM_N, EWRAP, CLK_BYP_N, CLK_VIEW, and
SDP_B[7]
Each internal PHY's analog signals including PHYREF, MDI +/-, and PHY_HSDACP/N
PCI Impedance Compensation ZPCOMP and ZNCOMP
Oscillator signals XTAL1 and XTAL2
Test signals including PHY_TSTPT and each PHY's HSDACP/N
Power-control pins CTRL_15, CTRL_25_A, and CTRL_25_B
SMB_ALERT_N/PCI_PWR_GOOD
All output drivers for all digital signal pins are disabled (with the exception of the TDO pin).
Analog signals such as MDI+/-, analog test points, and regulator controls are unaffected.
Dual-Mode
Name
Pin Name
0
TEST_DM_N
TEST_
MODE[3]
0
EWRAP
TEST_
MODE[2]
1
CLK_BYP_N
TEST_
MODE[1]
0
CLK_VIEW
TEST_
MODE[0]
1
SDP_B[7]
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