GD82551ER S L66X Intel, GD82551ER S L66X Datasheet - Page 25
GD82551ER S L66X
Manufacturer Part Number
GD82551ER S L66X
Description
Manufacturer
Intel
Datasheet
1.GD82551ER_S_L66X.pdf
(104 pages)
Specifications of GD82551ER S L66X
Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (min)
3V
Operating Supply Voltage (max)
3.6V
Operating Temperature Classification
Industrial
Package Type
BGA
Mounting
Surface Mount
Pin Count
196
Lead Free Status / Rohs Status
Not Compliant
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Figure 2. CSR I/O Read Cycle
5.2.1.1.1 Control/Status Register (CSR) Accesses
The 82551ER supports zero wait state single cycle memory or I/O mapped accesses to its CSR
space. Separate BARs request 4 KB of memory space and 64 bytes of I/O space to accomplish
these accesses. The 82551ER provides 4 valid KB of CSR space, which include the following
elements:
The following figures show CSR zero wait state I/O read and write cycles. In the case of accessing
the Control/Status Registers, the CPU is the initiator and the 82551ER is the target of the
transaction.
Read Accesses: The CPU, as the initiator, drives address lines AD[31:0], the command and byte
enable lines C/BE#[3:0] and the control lines IRDY# and FRAME#. As a slave, the 82551ER
controls the TRDY# signal and provides valid data on each data access. The 82551ER allows the
CPU to issue only one read cycle when it accesses the Control/Status Registers, generating a
disconnect by asserting the STOP# signal. The CPU can insert wait states by de-asserting IRDY#
when it is not ready.
•
•
•
•
•
•
System Control Block (SCB) registers
PORT register
Flash control register
EEPROM control register
MDI control register
Flow control registers
CLK
FRAME#
AD
C/BE#
IRDY#
TRDY#
DEVSEL#
STOP#
1
I/O RD
ADDR
2
3
BE#
DATA
4
5
6
Networking Silicon — 82551ER
7
8
9
17
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