GD82551ER S L66X Intel, GD82551ER S L66X Datasheet - Page 3
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GD82551ER S L66X
Manufacturer Part Number
GD82551ER S L66X
Description
Manufacturer
Intel
Datasheet
1.GD82551ER_S_L66X.pdf
(104 pages)
Specifications of GD82551ER S L66X
Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (min)
3V
Operating Supply Voltage (max)
3.6V
Operating Temperature Classification
Industrial
Package Type
BGA
Mounting
Surface Mount
Pin Count
196
Lead Free Status / Rohs Status
Not Compliant
Contents
1.0
2.0
3.0
4.0
5.0
Datasheet
Introduction......................................................................................................................... 1
1.1
1.2
1.3
1.4
Architectural Overview ....................................................................................................... 3
2.1
2.2
2.3
2.4
Performance Enhancements.............................................................................................. 5
3.1
3.2
3.3
3.4
Signal Descriptions.............................................................................................................7
4.1
4.2
4.3
4.4
4.5
4.6
Media Access Control Functional Description.................................................................. 15
5.1
5.2
5.3
5.4
5.5
5.6
Overview ............................................................................................................... 1
Byte Ordering ........................................................................................................ 1
References ............................................................................................................ 1
Product Ordering Codes........................................................................................ 2
Parallel Subsystem Overview................................................................................ 3
FIFO Subsystem Overview ................................................................................... 3
10/100 Mbps Serial CSMA/CD Unit Overview ......................................................4
10/100 Mbps Physical Layer Unit.......................................................................... 4
Multiple Priority Transmit Queues ......................................................................... 5
Early Release ........................................................................................................ 5
Hardware Integrity Support ................................................................................... 6
Management Data Interface MDI/MDI-X Feature.................................................. 6
Signal Type Definitions ......................................................................................... 7
PCI Bus Interface Signals ..................................................................................... 8
4.2.1
4.2.2
4.2.3
Local Memory Interface Signals .......................................................................... 10
Test Port Signals ................................................................................................ 11
PHY Signals ....................................................................................................... 12
Power and Ground Signals ................................................................................. 13
Device Initialization..............................................................................................15
5.1.1
PCI Interface ....................................................................................................... 16
5.2.1
5.2.2
5.2.3
PCI Power Management ..................................................................................... 25
5.3.1
5.3.2
Parallel Flash....................................................................................................... 30
Serial EEPROM Interface.................................................................................... 30
5.5.1
10/100 Mbps CSMA/CD Unit............................................................................... 32
5.6.1
5.6.2
5.6.3
5.6.4
Address and Data Signals ....................................................................... 8
Interface Control Signals ......................................................................... 8
System and Power Management Signals ............................................... 9
Initialization Effects................................................................................. 15
Bus Operations....................................................................................... 16
Clock Run Signal.................................................................................... 24
Power Management Event ..................................................................... 25
Power States .......................................................................................... 25
Wake-up Events ..................................................................................... 29
EEPROM Address Map.......................................................................... 32
Full Duplex ............................................................................................. 33
Flow Control ........................................................................................... 33
Address Filtering Modifications .............................................................. 33
VLAN Support ........................................................................................ 33
Networking Silicon — 82551ER
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