L-ET1011C2-CI-D LSI, L-ET1011C2-CI-D Datasheet - Page 5

• Manufacturer Part Number: L-ET1011C2-CI-D
• Manufacturer: LSI

Specifications of L-ET1011C2-CI-D

• Number Of Receivers: 1
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Lead Free Status / Rohs Status: Compliant

Oversampling Architecture
The ET1011C architecture uses oversampling techniques to
sample at two times the symbol rate. A fractionally spaced
feed forward equalizer (FFE) adapts to remove intersymbol
interference (ISI) and to shape the spectrum of the received
signal to maximize the (SNR) at the trellis decoder input.
The FFE equalizes the channel to a fixed target response.
Oversampling enables the use of a fractionally spaced equal-
izer (FSE) structure for the FFE, resulting in symbol rate
clocking for both the FFE and the rest of the receiver. This
provides robust operation and substantial power savings.
September 2007
Functional Description
The LSI ET1011C is a Gigabit Ethernet transceiver that simultaneously transmits and receives on each of the four UTP pairs of
category 5 cable (signal dimensions or channels A, B, C, and D) at 125 Msymbols/s using five-level pulse-amplitude modulation
(PAM). Figure 1 is a block diagram of its basic configuration.
LSI Corporation
PHYAD[4:0]
GTX_CLK
MDINT_N
RXD[7:0]
TXD[7:0]
RX_CLK
TX_CLK
RX_ER
RX_DV
TX_ER
TX_EN
Config
LEDS
MDIO
MDC
COL
CRS
RGMII
RTBI
GMII
Management
TBI
MII
Interface
Config
LEDS/
PCS
Cancellers
Figure 1. ET1011C Block Diagram
Decoder
Trellis
NEXT
MI Registers
Negotiation
Correction
Canceller
Auto-
Echo
BLW
Σ
Automatic Speed Downshift
Automatic speed downshift is an enhanced feature of autone-
gotiation that allows the ET1011C to:
n
n
n
For speed fallback, the ET1011C first tries to autonegotiate
by advertising 1000Base-T capability. After a number of
failed attempts to bring up the link, the ET1011C falls back
to advertising 100Base-TX and restarts the autonegotiation
process. This process continues through all speeds down to
10Base-T. At this point, there are no lower speeds to try and
so the host enables all technologies and starts again.
PHY configuration register, address 22, bits 11 and 10
enable automatic speed downshift and specifies if fallback to
10Base-T is allowed. PHY control register, address 23, bits
11 and 12 specify the number of failed attempts before
downshift (programmable to 1, 2, 3, or 4 attempts).
Fallback in speed, based on cabling conditions or link
partner abilities.
Operate over CAT-3 cabling (in 10Base-T mode).
Operate over two-pair CAT-5 cabling (in 100Base-TX
mode).
Transmit
Shaping
Control
Control
Timing
Gain
FFE
10BASE-T
DAC
ADC
Generator
Clock
Gigabit Ethernet Transceiver
PGA
Hybrid
PMA A
Bias
JTAG/
Clock
Reset
Test
PMA B
PMA B
PMA C
PMA D
TRD[0-3]±
RSET
TCK
TRST_N
TMS
TDI
TDO
SYS_CLK
XTAL_1
XTAL_2
RESET_N
5