AD8317-EVALZ Analog Devices Inc, AD8317-EVALZ Datasheet - Page 13

• Manufacturer Part Number: AD8317-EVALZ
• Manufacturer: Analog Devices Inc

Specifications of AD8317-EVALZ

• Lead Free Status / Rohs Status: Compliant

For example, P
terms of dBm (decibels referred to 1 mW), in a 50 Ω system is
For a square wave input signal in a 200 Ω system,
Further information on the intercept variation dependence
upon waveform can be found in the
data sheets.
SETTING THE OUTPUT SLOPE IN MEASUREMENT
MODE
To operate in measurement mode, VOUT must be connected
to VSET. Connecting VOUT directly to VSET yields the nominal
logarithmic slope of approximately −22 mV/dB. The output
swing corresponding to the specified input range is then approx-
imately 0.35 V to 1.7 V. The slope and output swing can be
increased by placing a resistor divider between VOUT and
VSET (that is, one resistor from VOUT to VSET and one
resistor from VSET to ground). The input impedance of VSET
is approximately 40 kΩ. Slope-setting resistors should be kept
below 20 kΩ to prevent this input impedance from affecting
the resulting slope. If two equal resistors are used (for example,
10 kΩ/10 kΩ), the slope doubles to approximately −44 mV/dB.
CONTROLLER MODE
The AD8317 provides a controller mode feature at the VOUT
pin. By using V
AD8317 to control subsystems, such as power amplifiers (PAs),
variable gain amplifiers (VGAs), or variable voltage attenuators
(VVAs), that have output power that increases monotonically
with respect to their gain control signal.
To operate in controller mode, the link between VSET and
VOUT is broken. A setpoint voltage is applied to the VSET
input, VOUT is connected to the gain control terminal of the
VGA, and the RF input of the detector is connected to the
output of the VGA (usually using a directional coupler and
some additional attenuation). Based on the defined relationship
P
P
2 dBV − 10 × log
P
−1 dBV − 10 × log
INTERCEPT
INTERCEPT
INTERCEPT
[dBm] =
[dBV] − 10 × log
=
INTERCEPT
SET
for the setpoint voltage, it is possible for the
Figure 28. Increasing the Slope
AD8317
10
for a sinusoidal input signal expressed in
(50 × 10
10
[(200 Ω × 1 mW/1 V
VOUT
VSET
10
−3
(Z
) = 15 dBm
10kΩ
10kΩ
0
× 1 mW/1 V
AD8313
–44mV/dB
and
RMS
2
RMS
)] = 6 dBm
AD8307
2
) =
Rev. B | Page 13 of 20
(8)
between V
measurement mode, the AD8317 adjusts the voltage on VOUT
(VOUT is now an error amplifier output) until the level at the
RF input corresponds to the applied V
operates in controller mode, there is no defined relationship
between the V
that results in the correct input signal level appearing at
INHI/INLO.
For this output power control loop to be stable, a ground-
referenced capacitor must be connected to the CLPF pin. This
capacitor, C
current) to set the loop bandwidth and ensure loop stability.
Further details on control loop dynamics can be found in the
AD8315
Decreasing V
signal from the VGA, increases V
of the VGA must have a positive sense. A positive control
voltage to the VGA increases the gain of the device.
The basic connections for operating the AD8317 in an auto-
matic gain control (AGC) loop with the
Figure 30. The ADL5330 is a 10 MHz to 3 GHz VGA. It offers a
large gain control range of 60 dB with ±0.5 dB gain stability.
This configuration is similar to Figure 29.
The gain of the ADL5330 is controlled by the output pin of the
AD8317. This voltage, V
avoid overdrive recovery issues, the AD8317 output voltage can
be scaled down using a resistive divider to interface with the 0 V
to 1.4 V gain control range of the ADL5330.
A coupler/attenuation of 21 dB is used to match the desired
maximum output power from the VGA to the top end of the
linear operating range of the AD8317 (approximately −5 dBm
at 900 MHz).
data sheet.
OUT
FLT
ATTENUATOR
DIRECTIONAL
SET
, integrates the error signal (in the form of a
and the RF input signal when the device is in
SET
COUPLER
, which corresponds to demanding a higher
and the V
52.3Ω
Figure 29. Controller Mode
OUT
47nF
47nF
OUT
, has a range of 0 V to near V
INHI
INLO
voltage; V
AD8317
VGA/VVA
OUT
VOUT
CLPF
. The gain control voltage
GAIN
CONTROL
VOLTAGE
VSET
C
SET
FLT
ADL5330
. When the AD8317
OUT
settles to a value
RFIN
DAC
are shown in
AD8317
POS
. To