SAE81C91NE13 Infineon Technologies, SAE81C91NE13 Datasheet - Page 20

• Manufacturer Part Number: SAE81C91NE13
• Manufacturer: Infineon Technologies

Specifications of SAE81C91NE13

• Number Of Transceivers: 1
• Power Down Mode: Sleep
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.5V
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 28
• Lead Free Status / Rohs Status: Not Compliant

Mode/Status-Register
MOD
Address: 10
Reset Value: 00
Bit(field)
IM
RES
BS
RWL
TWL
TC
RS
ADE
Semiconductor Group
H
H
Function
Init Mode
’0’:
’1’:
Reset Request
’0’:
’1’:
Bus State (read only)
’0’:
’1’:
Receiver Warning Level (read only)
’0’:
’1’:
Transmit Warning Level (read only)
’0’:
’1’:
Transmission Complete (read only)
’0’:
’1’:
Receive State (read only)
’0’:
’1’:
Auto Decrement Enable
’0’:
’1’:
ADE
Normal mode.
Initialization mode:
write access to the configuration registers BL1, BL2, OC, BRP is enabled.
If the bit stays set, the chip enters the normal mode, with enabled access to
the configuration registers.
If this bit is set in conjunction with bit RES a hard software reset is
activated.
Normal mode.
The chip enters the reset state:
– if bit IM = ’0’ a soft software reset takes place.
– if bit IM = ’1’ a hard software reset takes place. Further details see below.
Normal mode.
Bus Off state, the IC does not participate in bus activities.
Receive-error counter below 96.
Receive-error counter equal or above 96.
Transmit-error counter below 96.
Transmit-error counter equal or above 96.
The last transmission request is not yet executed successfully.
The last transmission request was executed successfully.
No reception active.
Currently the SAE 81C90/91 is in receive mode.
No automatic address decrement.
With every read or write access using the serial synchronous interface SI
the address is automatically decremented by one. So data can be
accessed sequentially without the need of writing a new address.
rw
7
07Feb95@09:05h Intermediate Version
RS
6
r
TC
5
r
19
TWL
4
r
RWL
3
r
BS
2
r
SAE 81C90/91
RES
rw
1
IM
rw
0