PEF80912HV14ZT Lantiq, PEF80912HV14ZT Datasheet - Page 22

• Manufacturer Part Number: PEF80912HV14ZT
• Manufacturer: Lantiq

Specifications of PEF80912HV14ZT

• Lead Free Status / Rohs Status: Supplier Unconfirmed

2.2
The IOM
Guide [13].
2.2.1
The IOM
indicates the start of an IOM
transfer on both data lines DU and DD. The DCL is twice the bit rate. The bits are shifted
out with the rising edge of the first DCL clock cycle.
Note: It is not possible to write any data via IOM
The IOM
The FSC signal is an 8 kHz frame sync signal. The number of PCM timeslots on the
transmit line is determined by the frequency of the DCL clock, with the 512 kHz clock 1
channel consisting of 4 timeslots is available.
IOM
The frame structure on the IOM
clock of 512 kHz is shown in
•
Figure 4
The frame is composed of one channel:
Channel 0 contains 144-kbit/s of user and signaling data (2B + D), a MONITOR
programming channel (not available in Q-SMINT
(CI0) for control of e.g. the U-transceiver.
Data Sheet
®
-2 Frame Structure of the Q-SMINT



-2 interface consists of four lines: FSC, DCL, DD, DU. The rising edge of FSC
-2 interface always operates in NT mode according to the IOM
-2 interface can be enabled/disabled with pin DIO.
IOM -2 Interface
IOM
IOM -2 Frame Structure of the Q-SMINT

-2 Functional Description
Figure

-2 frame. The DCL clock signal synchronizes the data

-2 data ports (DU,DD) of the Q-SMINT
4.
14

O


O) and a command/indication channel
-2 into the Q-SMINT

O
Functional Description
PEF 80912/80913

O.


O with a DCL
-2 Reference
2001-03-29