PEF80902HV11XT Infineon Technologies, PEF80902HV11XT Datasheet - Page 44

• Manufacturer Part Number: PEF80902HV11XT
• Manufacturer: Infineon Technologies

Specifications of PEF80902HV11XT

• Lead Free Status / Rohs Status: Compliant

•
Figure 11
As can be seen from the transition criteria, combinations of multiple conditions are
possible as well. A “ ” stands for a logical AND combination. And a “+” indicates a logical
OR combination.
Test Signals
• 2 kHz Single Pulses (TM1)
• 96 kHz Continuous Pulses (TM2)
Note: The test signals TM1 and TM2 can be generated via pins TM0-2 according to
Reset States
After an active signal on the reset pin RST the S-transceiver state machine is in the reset
state.
C/I Codes in Reset State
In the reset state the C/I code 0000 (TIM) is issued. This state is entered after a hardware
reset (RST).
C/I Codes in Deactivated State
If the S-transceiver is in state ‘Deactivated‘ and receives i0, the C/I code 0000 (TIM) is
issued until expiration of the 8 ms timer. Otherwise, the C/I code 1111 (DI) is issued.
Receive Infos on S/T
I0
Data Sheet
One pulse with a width of one bit period per frame with alternating polarity.
Continuous pulses with a pulse width of one bit period.
Table
INFO 0 detected
5.
State Diagram Notation
IOM-2 Interface
C/I code
S/T Interface
INFO
OUT
Ind. Cmd.
i
x
S ta te
IN
i
r
36
Unconditional
Transition
macro_17.vsd
Functional Description
PEF 80902
2001-11-12