GCIXP1240AB 837151 Intel, GCIXP1240AB 837151 Datasheet - Page 34

• Manufacturer Part Number: GCIXP1240AB 837151
• Manufacturer: Intel

Specifications of GCIXP1240AB 837151

• Lead Free Status / Rohs Status: Not Compliant

Intel
34
Table 15. IX Bus Interface Pins (Continued)
®
IXP1240 Network Processor
FBE_L[7:0]
TXASIS
RXFAIL
FAST_RX1
FAST_RX2
IX Bus Signal
Names
[30]
[29]
[28]
[27]
[26]
[25]
[24]
[23]
[22]
[21]
[20]
[19]
[18]
[17]
[16]
[15]
[14]
[13]
[12]
[10]
[11]
[9]
[8]
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
AL23
AJ22
AH21
AK22
AL22
AJ21
AH20
AK21
AL21
AJ20
AH19
AK20
AL20
AJ19
AK19
AL19
AJ18
AH17
AK18
AJ17
AK17
AL17
AH16
AJ16
AK16
AL16
AJ15
AH15
AK14
AJ14
AL13
AK13
AJ13
AL12
AK12
AH13
AJ12
AL11
AK11
AL10
AK10
AH11
AJ10
Pin #
I2/O5/
TS
O4/TS 1
I1/O1/
TS
I1
I1
Type
8
1
1
1
Total
Bidirectional Byte Enables.
64-bit bidirectional IX Bus mode. Bits [7:0] indicate transmit and
receive valid bytes on FDAT[63:0].
32-bit unidirectional IX Bus mode. Bits [7:4] are used to indicate
valid transmit bytes on FDAT[63:32] and bits [3:0] are used to
indicate valid receive bytes on FDAT[31:0].
In a shared IX Bus system, these pins will be tri-stated when
passing ownership of the IX Bus.
Transmit As Is/Transmit Error output.
TXASIS states are output according to values programmed in the
TFIFO control field. TXASIS value driven coincident with
SOP/SOP_TX signal.
In a shared IX Bus system, these pins will be tri-stated when
passing ownership of the IX Bus.
Receive Packet Failure. As input, asserted by a MAC device if a
packet was received with errors. Mimics the behavior of EOP to
terminate an IX Bus cycle.
As output, driven when no receive cycle in-progress.
In a shared IX Bus system, these pins will be tri-stated when
passing ownership of the IX Bus.
Ready Input from Fast Port 0 (i.e., Gigabit port). Pulldown through
10 KOhms to VSS if not used.
Ready Input from Fast Port 1 (i.e., Gigabit port). Pulldown through
10 KOhms to VSS if not used.
Pin Descriptions
Datasheet