CY7C53120E2-10SI Cypress Semiconductor Corp, CY7C53120E2-10SI Datasheet
CY7C53120E2-10SI
Specifications of CY7C53120E2-10SI
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CY7C53120E2-10SI Summary of contents
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... Addresses external memory (CY7C53150) ■ (CY7C53120E2 (CY7C53120E4) of ROM containing LonTalk network protocol firmware ■ Maximum input clock operation of 20 MHz (CY7C53150), 10 MHz (CY7C53120E2), 40 MHz (CY7C53120E4) over a –40°C to 85°C ■ 64-pin TQFP package (CY7C53150) ■ 32-pin SOIC or 44-pin TQFP package (CY7C53120) ...
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Contents Functional Description........................................................ 3 Pin Configurations .............................................................. 3 Pin Descriptions .................................................................. 5 Memory Usage ..................................................................... 6 Flash Memory Retention and Endurance.......................... 6 40 MHz 3120 Operation ....................................................... 6 Low Voltage Inhibit Operation............................................ 6 Communications Port ......................................................... 6 Programmable Hysteresis Values ...
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... The CY7C53150 Neuron chip is an exact replacement for the Motorola MC143150Bx and Toshiba TMPN3150B1 devices. The CY7C53120E2 Neuron chip is an exact replacement for the Motorola MC143120E2 device since it contains the same firmware in ROM. ...
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RESET IO4 3 30 IO5 IO3 4 29 IO6 IO2 5 28 IO7 IO1 6 27 IO8 IO0 7 26 IO9 SERVICE IO10 ...
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Pin Descriptions Pin Name I/O CLK1 Input Oscillator connection or external clock input. CLK2 Output Oscillator connection. Leave open when external clock is input to CLK1. Maximum of one external load. RESET I/O (Built-In Reset pin (active LOW). Note The ...
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Memory Usage All Neuron chips require system firmware to be present when they are powered up. In the case of the CY7C53120 family, this firmware is preprogrammed in the factory in an on-chip ROM. In the case of the CY7C53150, ...
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Programmable Hysteresis Values (Expressed as differential peak-to-peak voltages in terms of V [6] Hysteresis V Min V Typ hys hys 0 0.019 V 0.027 0.040 V 0.054 0.061 V 0.081 0.081 ...
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... LVI Trip Point ( Part Number CY7C53120E2, CY7C53120E4, and CY7C53150 Notes 11. Standard outputs are IO4–IO10, CP0, CP1, and CP4. (RESET is an open drain input/output. CLK2 must have < load.) For CY7C53150, standard outputs also include A0–A15, D0–D7, E, and R/W. 12. IO4–IO7 and SERVICE have configurable pull ups. RESET has a permanent pull up. ...
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External Memory Interface Timing — CY7C53150, V Parameter Description t Memory Cycle Time (System Clock Period) cyc [16] PW Pulse Width, E High EH [16] PW Pulse Width, E Low EL t Delay, E High to Address Valid AD t ...
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Figure 6. Drive Levels and Test Point Levels for Timing Specifications Unless Otherwise Specified DRIVE TO 2.4V DRIVE TO 0.4V A — Signal valid-to-signal valid specification (maximum or minimum) B — Signal valid-to-signal invalid specification (maximum or minimum) Figure 7. ...
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... CY7C53120E4-40AXI 4 Notes 23. All parts contain SRAM. 24. CY7C53120E2 firmware is bit-for-bit identical with Motorola MC143120E2 firmware. 25. CY7C53150 may be used with 20-MHz input clock only if the firmware in external memory is version 13 or later. 26. CY7C53120E4 requires upgraded LonBuilder® and NodeBuilder® software. Document #: 38-10001 Rev. *F ...
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Package Diagrams Figure 11. 44-Pin Thin Plastic Quad Flat Pack A44 12.00±0.25 SQ 10.00±0. SEATING PLANE 1.60 MAX. 0.10 0.20 MAX. Document #: 38-10001 Rev 0.37±0.05 STAND-OFF 0.05 MIN. 0.15 MAX. 0.80 ...
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Package Diagrams (continued) Figure 12. 64-Pin Thin Plastic Quad Flat Pack ( 1.4 mm) A64SA 16.00±0.25 SQ 14.00±0. SEATING PLANE 1.60 MAX. 0.10 0.20 MAX Document #: 38-10001 Rev. *F NOTE: 1. ...
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Package Diagrams (continued 0.793[20.142] 0.817[20.751] 0.101[2.565] 0.111[2.819] 0.050[1.270] BSC. 0.014[0.355] 0.020[0.508] Document #: 38-10001 Rev. *F Figure 13. 32-Pin (450-Mil) SOIC S32.45 1 DIMENSIONS IN INCHES[MM] PACKAGE WEIGHT 1.42gms 0.546[13.868] 0.566[14.376] 0.440[11.176] 0.450[11.430] 32 0.006[0.152] 0.012[0.304] 0.118[2.997] MAX. ...
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... Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement ...