RPIXP2850BB Intel, RPIXP2850BB Datasheet - Page 137

• Manufacturer Part Number: RPIXP2850BB
• Manufacturer: Intel

Specifications of RPIXP2850BB

• Operating Supply Voltage (typ): 1.3/1.5/2.5/3.3V
• Operating Supply Voltage (max): 1.575/2.7/3.465V
• Operating Supply Voltage (min): 1.235/2.3/3.135V
• Mounting: Surface Mount
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Not Compliant

Example 2.
Example 3.
7.1.2.2.2
Hardware Design Guide
Microprocessor Address Latch Logic
// implementation of 25-bit address packing control logic
always @(posedge sp_clk) begin
end // always @ (posedge sp_clk)
always @(posedge sp_clk) begin
end // always @ (posedge sp_clk)
In
Another method would be to define the latched_add register to be 32 bits, dropping any unused
upper bits; then ale_cnt would not be needed.
Microprocessor Address Latch Logic Without ale_cnt
// implementation of 32-bit address packing logic
always @(posedge sp_clk) begin
end // always @ (posedge sp_clk)
Data Multiplexing and Demultiplexing
The microprocessor interface supports 8-, 16-, and 32-bit devices while the flash interface supports
only 8-bit devices. This functionality requires that the SP_AD data bus be
multiplexed/demultiplexed to support read and write transactions. Additionally, there are four
Example
if (~rst_l) begin
end
else begin
end // else: !if(~rst_l)
if (~rst_l) begin
end
else begin
end // else: !if(~rst_l)
if (~rst_l) begin
end
else begin
end // else: !if(~rst_l)
ale_cnt
if (~sp_ale_l)begin
end
else if (sp_ale_l) begin
end
latched_add
if (~sp_ale_l) begin
end
latched_add
if (~sp_ale_l) begin
end
2, we use a two-bit count, ale_cnt, to steer the data into the appropriate byte-lane.
ale_cnt
ale_cnt
case (ale_cnt)
2'b00:
2'b01:
2'b10:
2'b11:
endcase // case(ale_cnt)
latched_add[7:0]
latched_add[15:8]
latched_add[23:16]
latched_add[31:24]
<= 2'b00;
latched_add[7:0]
latched_add[15:8]
latched_add[23:16]
latched_add[24]
<= ale_cnt + 1;
<= 2'b00;
<= 25'h0000000;
<= 32'h00000000;
//synopsys full_case parallel_case
<= sp_ad_in;
<= latched_add[7:0];
<= latched_add[15:8];
<= latched_add[23:16];
Example 3
<= sp_ad_in;
<= sp_ad_in;
<= sp_ad_in;
<= sp_ad_in[0];//for 25-bit address space
shows a coded example of this logic.
IXP28XX Network Processor
Slowport
137