RPIXP2850BB Intel, RPIXP2850BB Datasheet - Page 63

• Manufacturer Part Number: RPIXP2850BB
• Manufacturer: Intel

Specifications of RPIXP2850BB

• Operating Supply Voltage (typ): 1.3/1.5/2.5/3.3V
• Operating Supply Voltage (max): 1.575/2.7/3.465V
• Operating Supply Voltage (min): 1.235/2.3/3.135V
• Mounting: Surface Mount
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Not Compliant

Table 18.
1.
4.4.4
Hardware Design Guide
QDRn_Q_H[16:9]
QDRn_Q_H[8]
QDRn_Q_H[7:0]
QDRn_Q_H[8]
QDRn_D_H[16:9]
QDRn_D_H[17]
QDRn_D_H[7:0]
QDRn_D_H[8]
QDRn_RPS_L[0]
QDRn_WPS_L[0]
QDRn_RPS_L[1]
QDRn_WPS_L[0]
QDRn_BWS_L[0]
QDRn_BWS_L[1]
V
V
QDRn_ZQ[1:0]
VREF_QDRn
IXP28XX Signals
DDQ
DD_Core
Termination is not required for all topologies. Signal Integrity simulations should be performed to determine if the termination is required.
= 1.5
=1.3 V
QDR SRAM Signal Mapping (Sheet 2 of 2)
ClamShell Configuration of SRAMs
When it is necessary to use more than one SRAM device to achieve a certain memory size capacity,
the SRAMs can be arranged in either a Width-Expansion configuration or a Depth-Expansion
configuration. Clam-shelling—that is, locating two devices on opposite sides of the PCB—is
possible in either case of width-expansion or depth-expansion. However, it is important to check
whether the particular signal addressed is properly mirrored or no in the SRAM part used so that it
can be routed properly. If it is not mirrored then the signal can be routed as is where one SRAM is
–
–
Q[7:0]
Q[8]
–
–
D[7..0]
D[8]
R#
W#
–
–
BW#
–
V
V
1.8 V
Z
GND
V
Top SRAM 1
Q
ref
DDQ
DD_Core
=250Ω to
=0.75
(2Mx9)
=1.5 V
=
–
–
Q[7:0]
Q[8]
–
–
D[7..0]
D[8]
–
–
R#
W#
BW#
–
V
V
1.8 V
Z
GND
V
Bottom SRAM 2
DDQ
DD_Core
Q
ref
=250Ω to
=0.75
(2Mx9)
=1.5 V
=
–
–
On-die at
IXP28XX
Receiver
On-die at
IXP28XX
Receiver
–
–
PU50Ω
PU50Ω
–
–
–
–
PU35Ω
–
–
–
–
–
Termination
V
TT
=0.75 V
Q[7:0]
Q[8]
D[7:0]
D[8]
R#
W#
–
–
–
–
–
–
–
BW#
V
V
1.8 V
Z
GND
V
Top SRAM 3
Q
ref
DDQ
DD_Core
=250Ω to
=0.75
(2Mx9)
=1.5 V
=
IXP28XX Network Processor
Bottom SRAM 4
Q[7:0]
Q[8]
–
–
D[7:0]
D[8]
–
–
–
–
R#
W#
–
BW#
V
V
1.8 V
Z
GND
V
Q
DDQ
DD_Core
ref
=250Ω to
=0.75
(2Mx9)
=1.5 V
=
On-die at
IXP28XX
Receiver
On-die at
IXP28XX
Receiver
–
–
PU50Ω
PU50Ω
–
–
PU35Ω Center
Termination at
T-junction
PU35Ω Center
Termination at
T-junction
PU35Ω Center
Termination at
T-junction
PU35Ω
–
PU35Ω
–
–
–
–
Termination
QDR SRAM
V
TT
=0.75 V
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