RPIXP2800BC Intel, RPIXP2800BC Datasheet - Page 71
RPIXP2800BC
Manufacturer Part Number
RPIXP2800BC
Description
Manufacturer
Intel
Datasheet
1.RPIXP2800BC.pdf
(154 pages)
Specifications of RPIXP2800BC
Operating Supply Voltage (typ)
1.3/1.5/2.5/3.3V
Operating Supply Voltage (max)
1.575/2.7/3.465V
Operating Supply Voltage (min)
1.235/2.3/3.135V
Mounting
Surface Mount
Operating Temperature (max)
70C
Operating Temperature (min)
0C
Operating Temperature Classification
Commercial
Lead Free Status / Rohs Status
Not Compliant
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Figure 33.
Table 24.
4.5.5
Hardware Design Guide
1.
Figure 33
QDR Q Signal Trace Width/Spacing Routing
Table 24
QDR Q Stack-up Signal Cross-section Details
QDR SRAM K, K# Clock Topologies
The K input clock registers address and control inputs on the rising edge. Data is registered on the
rising edge of K and the rising edge of K#, which is ideally 180 degrees out of phase with K. All
synchronous inputs must meet setup and hold times around the clock’s rising edges.
The K-Clock signals have 2 SRAM loads and the signals are mirrored in the SRAM part. Thus, the
topology of choice for the K-Clocks is a point-to-point topology with two SRAMs clam-shelled.
Figure 34
Parameter
Value
P refers to the package length.
T
signal
lists the QDR Q stack-up signal cross-section details.
T
T
illustrates routing for QDR Q signal trace width/spacing.
illustrates the routing topology for QDR K and K#.
d2
d1
Signal
QDR
Q
Signals
Other
Width (W)
[mils]
Trace
5
Thickness
(Tsignal)
20 mil or larger
[mils]
Trace
0.5
Prepreg
POWER or GND Plane
POWER or GND Plane
(S) [mils]
Spacing
20 - 25
Trace
Thickness
[mils]
(TD1)
Signal
DATA
D1
5.0
W
Thickness
IXP28XX Network Processor
[mils]
(Td2)
5.7
D2
S
Er(D1) Er(D2)
3.5
Signal
DATA
W
3.8
QDR SRAM
D2
D1
B3992-01
between
Spacing
groups
20 - 25
signal
[mils]
71
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