RPIXP2800BC Intel, RPIXP2800BC Datasheet - Page 94
RPIXP2800BC
Manufacturer Part Number
RPIXP2800BC
Description
Manufacturer
Intel
Datasheet
1.RPIXP2800BC.pdf
(154 pages)
Specifications of RPIXP2800BC
Operating Supply Voltage (typ)
1.3/1.5/2.5/3.3V
Operating Supply Voltage (max)
1.575/2.7/3.465V
Operating Supply Voltage (min)
1.235/2.3/3.135V
Mounting
Surface Mount
Operating Temperature (max)
70C
Operating Temperature (min)
0C
Operating Temperature Classification
Commercial
Lead Free Status / Rohs Status
Not Compliant
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IXP28XX Network Processor
QDR SRAM
Figure 57.
4.11
94
QDR Signal Tee Point Arms Routed on Signal Layers 4 and 13
QDR SRAM Design Review Checklist
Use the following design review checklist for QDR SRAM schematic reviews:
QDR signal Tee Point arms routed on signal layers 4 and 13
•
•
•
•
•
•
For clamshell pairs, the data bus pins are flipped, so the BWS_N signals also must be flipped.
The byte parity is DQ8 for byte 0.
The byte parity is DQ17 for byte 1.
Check for proper ZQ resistor: 50 Ω.
QDR JTAG pins are 3.3 V on the IXP28XX network processor, but 1.5 V on QDR devices,
i.e., a level-shift is necessary.
The IXP28XX network processor CIN[1] pins are NC from the I/O pad to the SRAM
controller internally. Only CIN[0] is used to derive the read capture clock.
— The CIN[1] pin can be used to terminate the clock and this I/O pad is controllable via the
RCOMP registers. Refer to the Intel® IXP2400 and IXP2800 Network Processor
Programmer’s Reference Manual for more details.
Hardware Design Guide
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