HI5960IAZ-T Intersil, HI5960IAZ-T Datasheet - Page 9

• Manufacturer Part Number: HI5960IAZ-T
• Description: CONV D/A 14BIT 130MSPS 28-TSSOP
• Manufacturer: Intersil

Specifications of HI5960IAZ-T

• Settling Time: 35ns
• Number Of Bits: 14
• Data Interface: Parallel
• Number Of Converters: 1
• Voltage Supply Source: Analog and Digital
• Power Dissipation (max): 200mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 28-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: HI5960IAZ-TTR

corresponding components should be located over the
digital ground plane and terminated to the digital ground
plane. The same is true for the analog components and the
analog ground plane. Consult Application Note 9853.
Noise Reduction
To minimize power supply noise, 0.1µF capacitors should be
placed as close as possible to the converter’s power supply
pins, AV
using separate digital and analog ground planes and these
capacitors should be terminated to the digital ground for
DV
filtering of the power supplies on the board is recommended.
Voltage Reference
The internal voltage reference of the device has a nominal
value of +1.2V with a ±60ppm/
full temperature range of the converter. It is recommended
that a 0.1µF capacitor be placed as close as possible to the
REFIO pin, connected to the analog ground. The REFLO pin
(16) selects the reference. The internal reference can be
selected if pin 16 is tied low (ground). If an external
reference is desired, then pin 16 should be tied high (the
analog supply voltage) and the external reference driven into
REFIO, pin 17. The full scale output current of the converter
is a function of the voltage reference used and the value of
R
though operation below 2mA is possible, with performance
degradation.
If the internal reference is used, V
approximately 1.2V (pin 18). If an external reference is used,
V
I
I
If the full scale output current is set to 20mA by using the
internal voltage reference (1.2V) and a 1.91kΩ R
resistor, then the input coding to output current will resemble
the following:
Outputs
IOUTA and IOUTB are complementary current outputs. The
sum of the two currents is always equal to the full scale
output current minus one LSB. If single ended use is
desired, a load resistor can be used to convert the output
current to a voltage. It is recommended that the unused
output be either grounded or equally terminated. The voltage
developed at the output must not violate the output voltage
compliance range of -0.3V to 1.25V. R
OUT
OUT
INPUT CODE (D13-D0)
SET
FSADJ
DD
1111 11111 11111
1000 00000 00000
0000 00000 00000
(Full Scale) = (V
(Full Scale) is:
. I
and to the analog ground for AV
TABLE 1. INPUT CODING vs OUTPUT CURRENT
OUT
DD
will equal the external reference. The calculation for
and DV
should be within the 2mA to 20mA range,
DD
FSADJ
. Also, the layout should be designed
IOUTA (mA)
/R
SET)
9
o
20
10
C drift coefficient over the
0
FSADJ
X 32.
LOAD
DD
will equal
. Additional
(the impedance
IOUTB (mA)
SET
10
20
0
HI5960
loading each current output) should be chosen so that the
desired output voltage is produced in conjunction with the
output full scale current. If a known line impedance is to be
driven, then the output load resistor should be chosen to
match this impedance. The output voltage equation is:
V
These outputs can be used in a differential-to-single-ended
arrangement to achieve better harmonic rejection. The
SFDR measurements in this data sheet were performed with
a 1:1 transformer on the output of the DAC (see Figure 1).
With the center tap grounded, the output swing of pins 21
and 22 will be biased at zero volts. The loading as shown in
Figure 1 will result in a 500mV signal at the output of the
transformer if the full scale output current of the DAC is set
to 20mA.
V
center tap to float will result in identical transformer output,
however the output pins of the DAC will have positive DC
offset. Since the DAC’s output voltage compliance range is -
0.3V to +1.25V, the center tap may need to be left floating or
DC offset in order to increase the amount of signal swing
available. The 50Ω load on the output of the transformer
represents the spectrum analyzer’s input impedance.
R
LOADING EACH OUTPUT
OUT
OUT
EQ
IS THE IMPEDANCE
HI5960
PIN 21
PIN 22
= I
= 2 x I
OUT
OUT
X R
x R
LOAD
IOUTB
IOUTA
EQ
.
, where R
FIGURE 1.
100Ω
50Ω
50Ω
EQ
is ~12.5Ω. Allowing the
V
OUT
50Ω REPRESENTS THE
SPECTRUM ANALYZER
= (2 x I
50Ω
OUT
x R
EQ
)V