LTC4245CUHFTR Linear Technology, LTC4245CUHFTR Datasheet - Page 26

• Manufacturer Part Number: LTC4245CUHFTR
• Manufacturer: Linear Technology

Specifications of LTC4245CUHFTR

• Family Name: LTC4245
• Package Type: QFN EP
• Operating Supply Voltage (min): 2.25/4.25/10.2/-10.2V
• Operating Supply Voltage (max): 0/10/20/-20V
• Operating Temperature (min): 0C
• Operating Temperature (max): 70C
• Operating Temperature Classification: Commercial
• Product Depth (mm): 5mm
• Product Length (mm): 7mm
• Mounting: Surface Mount
• Pin Count: 38
• Lead Free Status / Rohs Status: Not Compliant

APPLICATIO S I FOR ATIO
LTC4245
Table 2. Sense Resistance Values
If necessary, two resistors with the same tolerance can
be connected in parallel to yield the 3.5mΩ and 2.5mΩ
values.
2. Select the SS capacitor for limiting the rate of rise of
inrush current. Equations 1 and 2 lead to the following
design equation:
Applying Equation 6 to the 12V supply, with G
I
of 150mA/ms yields a C
capacitance value satisfi es the dI/dt requirements of the
other supplies too. Hence, a 220nF (±10%) capacitor is
chosen for C
3. To determine the TIMER capacitance, the time required
to completely power-up all supply outputs simultaneously
needs to be calculated. There are three parts to this time:
time for the internal current limit to cross zero (t
for the gate to slew to the MOSFET threshold voltage (t
and the time for the current fl ow to charge up the load
capacitors (t
t
zero is simply:
t
rise to the threshold voltage depends on I
the gate charge required to turn on the external MOSFET.
A typical value for this time is 1ms. This can be verifi ed
after the MOSFETs are selected. Since the current limit
ramp is almost stopped while any MOSFET is turning on,
t
the four MOSFET turn-ons overlaps in time.
26
SS(MAX)
1
2
2
: The maximum time for the gate of the external MOSFET to
: The time for the internal current limit to rise above
is 4 times 1ms or 4ms, since in the worst case none of
C
t
SUPPLY
1
SS MIN
–12V
3.3V
= •
12V
5V
(
4
of 24μA, R
( / )
)
dI dt
≥
I
3
SS
FBL MIN
) (see Figure 17).
R
.
SENSE MIN
(
R
SENSE
(
100mΩ
3.5mΩ
2.5mΩ
MIN
50mΩ
SENSE(MIN)
U
)
G
(
(1%)
SS
)
SS(MIN)
•
)
U
I
SS MAX
•( / )
dI dt
(
of 49.5mΩ, and (dI/dt)
I
greater than 149nF. This
TRIP(MIN)
891mA
396mA
6.4A
8.9A
)
W
(
MA
X X )
GATE(UP)(MIN)
SS
I
of 46mV/V,
TRIP(MAX)
U
606mA
11.1A
1.1A
7.9A
1
), time
(MAX)
and
(6)
(7)
2
)
t
fects the inrush current profi le. To simplify calculations, the
inrush current profi le shown in Figure 17 is chosen. All the
current is assumed to charge the load capacitor, i.e., there
is no load current. There are four parts to t
Equations 8 to 11 are used to determine t
⎛
⎜
⎜
⎜
⎝
t
3
34
: Under simultaneous power-up each output voltage af-
0
C
I
I
I
NEG
FBH
FBL
,
t
t
t
L
0
31
32
33
=
• (
Figure 17. Inrush Current Profi le for Design Example
max
INTERNAL CURRENT LIMIT
INRUSH CURRENT FOR LARGER C
INRUSH CURRENT FOR SMALLER C
=
=
= min
V
( / )
OUT
I
C
dI dt
FBL MIN
t
V
I
L
1
FBL MIN
GATE
•
(
⎛
⎜
⎜
⎜
⎜
⎜
⎝
–
V
V
(
I
GATE
= 0
FBH MIN
FB
V
t
(
FB
2
2
)
MIN
( / )
= V
(
– . •
•
)
) – . •
dI dt
t
C
31
TH
0 5
)
( / )
L
dI dt
0 5
)
• • (
I
–
FBH MIN
V
t
I
(
FBL MIN
31
MIN
OUT
t
(
t
33
32
(
L
MIN
(
L
)
V
• (
–
)
OUT
)
I
V
FBL MIN
)
FB
= V
,
)
FB
(
t
33
+
(SMALL C
OR
V
OUT
t
t
33
)
2
31
+
= V
31
I
IN
F F BH MIN
L
−
)
3
to t
t
as shown.
(LARGE C
31
(
V
t
OUT
34
34
⎞
⎟
⎟ ⎟
⎟
⎟
⎟
⎠
:
= V
)
)
(10)
4245 F17
IN
(11)
4245fa
L
⎞
⎟
⎟
⎟
⎠
(8)
(9)
)