PPC405EP-3LB200C Applied Micro Circuits Corporation, PPC405EP-3LB200C Datasheet - Page 33

• Manufacturer Part Number: PPC405EP-3LB200C
• Manufacturer: Applied Micro Circuits Corporation

Specifications of PPC405EP-3LB200C

• Family Name: 405EP
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 200MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.8V
• Operating Supply Voltage (max): 1.95V
• Operating Supply Voltage (min): 1.65V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 385
• Package Type: EBGA
• Lead Free Status / Rohs Status: Compliant

PPC405EP – PowerPC 405EP Embedded Processor
Table 6. Signal Functional Description (Sheet 3 of 6)
Secondary multiplexed signals are shown in brackets.
Notes:
1. Receiver input has hysteresis.
2. Must pull up. See “Pull-Up and Pull-Down Resistors” on page 29 for recommended termination values.
3. Must pull down. See “Pull-Up and Pull-Down Resistors” on page 29 for recommended termination values.
4. If not used, must pull up.
5. If not used, must pull down.
6. Strapping input during reset; pull up or pull down as required.
7. Pull-up may be required. See “External Bus Control Signals” on page 30.
AMCC
SDRAM Interface
External Slave Peripheral Interface
MemData00:31
MemAddr12:00
MemClkOut0:1
PerData00:15
PerAddr03:05
PerAddr06:31
Signal Name
PerWBE0:1
BankSel0:1
[PerCS1:4]
ClkEn0:1
DQM0:3
[PerWE]
PerCS0
PerR/W
PerOE
BA1:0
RAS
CAS
WE
Memory data bus.
Notes:
1. MemData00 is the most significant bit (msb).
2. MemData31 is the least significant bit (lsb).
Memory address bus.
Notes:
1. MemAddr12 is the most significant bit (msb).
2. MemAddr00 is the least significant bit (lsb).
Bank Address supporting up to 4 internal banks.
Row Address Strobe.
Column Address Strobe.
DQM for byte lane: 0 (MemData00:7),
Select up to two external SDRAM banks.
Write Enable.
SDRAM Clock Enable.
Two copies of an SDRAM clock allows, in some cases, glueless
SDRAM attach without requiring this signal to be repowered by a PLL
or zero-delay buffer.
Peripheral data bus.
Note: PerData00 is the most significant bit (msb) on this bus.
Peripheral address bus.
Note: PerAddr03 is the most significant bit (msb) on this bus.
These pins act as byte-enables which are valid for an entire cycle or
as write-byte-enables which are valid for each byte on each data
transfer, allowing partial word transactions.
Peripheral write enable. Low when either of the two PerWBE0:1 write
byte enables are low.
To access this function, software must toggle a DCR bit.
Peripheral chip select bank 0.
Four additional peripheral chip selects
To access this function, software must toggle a DCR bit.
Peripheral output enable.
Peripheral read/write. High indicates a read from memory, low
indicates a write to memory.
1 (MemData08:15),
2 (MemData16:23), and
3 (MemData24:31)
Description
Revision 1.08 – March 24, 2008
I/O
I/O
I/O
I/O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
5V tolerant
5V tolerant
5V tolerant
5V tolerant
5V tolerant
5V tolerant
5V tolerant
5V tolerant
Type
Data Sheet
Notes
1, 7
1
1
7
7
7
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