STV3550B STMicroelectronics, STV3550B Datasheet
STV3550B
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STV3550B Summary of contents
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Features ■ Fully-programmable DVO stage for direct RGB interface to flat display panel with 4- to 10-bit color resolution and pixel resolution from VGA to WXGA including HDTV2 ■ Versatile integrated up-converter – 50/60-Hz progressive output with line- interpolation (A ...
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Contents Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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STV3550 4.1.4 4.1.5 4.2 2D graphics accelerator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Contents 6.3.1 6.3.2 6.3.3 6.3.4 6.3.5 6.3.6 6.3.7 6.3.8 6.3.9 6.3.10 6.3.11 6.3.12 6.4 Reset strategy . . . . . . . . . . . . . . . . . . . . . . . . ...
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STV3550 7.5.1 7.5.2 7.6 Analog to digital converter (ADC ...
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Contents 7.8.4 7.8.5 7.8.6 7.9 IrDA encoder/decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... PQFP (0.5 mm pitch) package. The STV3550 completes the Digital IC Core family (STi5xxx, STi7xxx) which offers common CPU and software platforms based on STMicroelectronics’ 32-bit ST20 CPU core. This device, which is specifically designed for plasma or LCD TV applications, is completely compatible with the architecture and software of the STV3500 CTV100-CRT platform that targets CRT-based TV chassis ...
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Description Figure 2. CTV100-LCD platform example RGB CVBS RGB CVBS SCART SCART TEA6415C Bus-controlled Digital Video Decoder Video Matrix and Output Scaler Picture/Sound Tuner Intermediate Frequency *one or two banks 1.1 Software The layering model adopted for the CTV100-LCD software ...
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STV3550 The CTV100-LCD application software consists of 4 main layers based on these non- functional requirements: ● System layer provides certain general-purpose components such as handle or link list managers. this layer also contains the operating system abstraction layer (OSAL) ...
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Description 1.2.2 User guides A user guide is provided for each set of selected features. These documents will enable the user to get started with the relevant features. An example code is also included as well as a troubleshooting section. ...
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STV3550 2 Pin list 2.1 Pin out Figure 5. Pinout diagram 156 PORTC0 157 PORTA0 PORTD4 PORTA1 PORTD7 PORTA4 VDD33_IO PORTA5 PORTA6 PORTA7 VDD33_IO VSS_IO PORTD5 PORTC7 PORTC6 PORTC5 PORTC4 PORTD0 PORTD1 PORTD2 PORTD3 VDD33_IO PORTD6 PORTA2 PORTA3 VSS_IO PORTB5 ...
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Pin list 2.2 Pin description Table 1. DVI stage Pin number 140 141 142 143 144 145 146 147 148 149 150 Table 2. DVO stage Pin number Digital 193 194 195 202 203 204 205 206 208 1 2 ...
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STV3550 Table 2. DVO stage (continued) Pin number 196 197 Table 3. Parallel input/output pins Pin number 158 PORTA0 160 PORTA1 180 PORTA2 181 PORTA3 ...
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Pin list Table 3. Parallel input/output pins (continued) Pin number 183 PORTB5 157 PORTC0 156 PORTC1 155 PORTC2 154 PORTC3 173 PORTC4 172 PORTC5 171 PORTC6 170 PORTC7 174 PORTD0 175 PORTD1 176 PORTD2 177 PORTD3 159 PORTD4 169 PORTD5 ...
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STV3550 Table 4. External memory interface pins (continued) Pin number 96 FLASH_D14 94 FLASH_D15 SDRAM data bus 42 SDRAM_D0 41 SDRAM_D1 40 SDRAM_D2 39 SDRAM_D3 38 SDRAM_D4 37 SDRAM_D5 36 SDRAM_D6 35 SDRAM_D7 52 SDRAM_D8 51 SDRAM_D9 50 SDRAM_D10 49 ...
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Pin list Table 4. External memory interface pins (continued) Pin number 77 ADDR_15 75 ADDR_16 88 ADDR_17 89 ADDR_18 90 ADDR_19 Controls 81 RD_NOTWR 87 NOT_CS_FLASH 78 NOT_CS_SDRAM 79 NOT_RAS 80 NOT_CAS 82 NOT_BE0 57 NOT_BE1 66 CKOUT_SDRAM 69 CKIN_SDRAM ...
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STV3550 Table 6. Power supplies Pin number Analog 192 139 190 191 133 134 129 130 127 128 138 137 Digital 106 115 124 151 163 167 178 189 201 207 ...
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Pin list Table 6. Power supplies (continued) Pin number 105 116 125 153 168 182 199 200 117 126 152 198 Table 7. Not connected Pin ...
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STV3550 2.3 Parallel I/O pins and alternate functions The STV3550 includes 30 parallel I/O pins arranged in four banks 8-bit ports. The pins can be programmable in input, output, bi-directional or as alternate function pins. The ports ...
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Video function description 3 Video function description 3.1 Standard definition input (SDIN) The standard definition input (SDIN) processes video signals before their storage in the external SDRAM. The SDIN includes the following features and functions: ● 4:2:2 D1 input stream ...
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STV3550 includes VBI data such as Teletext, closed caption, WSS, VPS, and sync pulses for horizontal and vertical synchronization. The ancillary data is stored aligned in 32-bit packets. If necessary, the packets are completed by a filler with programmable data ...
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Video function description The vertical filter line-memories are limited to 720 pixels. When a line exceeds 720 pixels, the input line must be truncated to 720 pixels by the D1 interface (configured at 720 pixels per line). 3D temporal noise ...
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STV3550 3.2.2 De-interlacing modes and progressive scan output The de-interlacing can be done in the following modes: ● Spatial line interpolation, using the high resolution vertical polyphase filter ● Motion adaptive spatial-temporal interpolation, using the median filter ● Field merging ...
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Video function description 3.2.3 Regulation modes The regulation modes of the input and output dataflows are based on the configurations of several blocks such as the SDIN, VTG, Display, and also depends on the selected synchronization modes. These regulation modes ...
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STV3550 Figure 8. Video display flowchart Domain System Clock VTG Display Clock Domain Pixel Clock Domain All data is in Analog Y/Cr/Cb format STBus Interconnect T2 Memory Interface Pan/Scan Luma Path HFC/VFC PSI Line Buffer 4:2:2 to 4:4:4 Up-Conversion Pixel ...
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Video function description 3.3.1 Main features ● Horizontal resizing using a sample rate converter based on an 8-tap, 32-phase polyphase filter with a programmable factor from 0. ● Vertical resizing using a sample rate converter based on a ...
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STV3550 The rescaling function is performed by two 32-phase polyphase filters (Horizontal and Vertical), of which all coefficients are stored in a programmable table. In this case, if needed, the transfer function of the filter can be optimized by referring ...
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Video function description Figure 11. Display formats for 4:3 input, 16:9 aspect ratio (letter-box) and 16:9 TV screen No Zoom Figure 12. Display formats for 4:3 input, 2:35 aspect ratio (wide film) and 16:9 TV screen No Zoom Figure 13. ...
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STV3550 Figure 14. Image improvement block diagram Input Stage Filtering Brightness Yin Estimator Histogram Autoformat Detection Chrominance Processing Cbin, Crin 3.3.4 Brightness estimator The Brightness Estimator provides the value of the average field brightness of the picture. It can be ...
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Video function description Figure 15. Yce = Ylp + Yg ● The inflexion point is dependant either on the average brightness (when using brightness estimator values) or the input value (when using manual mode). ● The range parameter modifies the ...
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STV3550 Table 9. Gain factor Gain parameter Black stretch The black stretch algorithm is used to decrease the black part under the average brightness point. The inflection point is based on the average brightness, but another value can be set ...
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Video function description White stretch The white stretch algorithm is used on a dark sequence in order to increase the contrast on the entire image. By default, the inflexion point is based on the average brightness, but another value can ...
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STV3550 Figure 20. White stretch 2 Figure 21 shows the special case of range values and 3 in which the inflexion point is set by the user and is not based on the value of the average ...
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Video function description Grey stretch In grey stretch mode, the black and white stretch values are combined to increase the contrast in both the black and white parts of the image. This function decreases the black level in the dark ...
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STV3550 Figure 23. Grey stretch algorithm with maximum gain Black and white shrink The black and white shrink function increases the black level in the dark part of the picture and decreases the white level in the bright part while ...
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Video function description Figure 24. Black and white shrink diagram 3.3.7 Spectral processing Adaptive peaking The luminance bandwidth must be improved when processing decoded composite signals and especially when a notch filter from the external digital video decoder is used. ...
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STV3550 3.3.8 Color transient improvement Color transient improvement (CTI) is used to improve color transitions and chroma resolution. It uses a custom filter to enhance chroma transitions. Overshoots and undershoots of correction are suppressed to eliminate incorrect colors at the ...
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Graphics functional description 4 Graphics functional description Note: Some descriptions in this section are not applicable for LCD applications. 4.1 On-screen display generator (OSD) 4.1.1 General information The on-screen display (OSD) unit is used to overlay the video image with ...
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STV3550 4.1.3 Functional description The OSD function displays a user-defined bitmap over any part of the displayable (i.e. non- blanked) screen, independent of the size and location of the active video area. This bitmap can be defined independently for each ...
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Graphics functional description Figure 27. Two display regions using the same display lines 4.1.4 Programming OSD display regions The characteristics of each OSD region are contained in an OSD specification which is stored in the 64-Mbit SDRAM. The following data ...
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STV3550 Figure 28. OSD specification First Specification Address register Topp[31:0] OSDp[31:0] Bottomp[31:0] SLL = 1 The OSD will stop at the end of Region 2. An OSD specification can be placed anywhere within the entire 64-Mbit SDRAM. Each OSD region ...
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Graphics functional description Figure 29. Linked list structure for OSD data First Specification Address register Palettep[31:0] Header 1 Palette Topp[31:0] Bottomp[31:0] OSDp[31:0] Header 2 Topp[31:0] OSDp[31:0] Bottomp[31:0] Palettep[31:0] Header 3 Palette Topp[31:0] Bottomp[31:0] STOP, if Stop Linked Lists bit is ...
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STV3550 Figure 30. Field storage formats Field-Based Format Header Free Space Palette Free Space Top Field Block Free Space Bottom Field Block Free Space Header format The header is a block of nine 32-bit words dedicated to a single specification ...
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Graphics functional description Note: The Palettep[31:0] value is not the address of the first byte of the first color in the palette the address of the first byte of the first color loaded in the OSD CLUT. The ...
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STV3550 Figure 31. OSD region positions Vsync Vertical Shift “X” TV lines N’ TV lines Horizontal Shift Hsync Color characteristics The address in the OSD color look-up-table (CLUT) (not in the SDRAM), where the color defined in the palette of ...
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Graphics functional description In this case, the OSD consists of two different images which are displayed one after the other at a rate of 50 images per second. The human eye is able to detect the appearance and disappearance of ...
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STV3550 This can be used to independently control the contrast of the OSD plane in relation to the video display plane. Table 12. OSD header characteristics Bit field PNDL[11:0] Gain[5:0] GaEn MiMo[1:0] FM[1:0] SLL NP Offset[9:0] CLUTAdd[7:0] NCL[7:0] MiW[7:0] Bits ...
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Graphics functional description Table 12. OSD header characteristics (continued) Bit field MiGa[8:0] TPND[21:0] Pitch[12:0] Y_top[10:0] Y_bottom[10:0] X_left[11:0] X_right[11:0] Palettep[31:0] Topp[31:0] Bottomp[31:0] OSDp[31:0] 48/145 Bits Mixing factor which multiply or divide the Alpha parameter when proportional mixing mode is selected. 9 ...
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STV3550 Color data Each color in the CLUT is defined using the RGB color elements and a mixing factor which determines the overlaying effect of the OSD ...
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Graphics functional description Each OSD specification after the first one can either use the same color palette as the previous OSD region new one can be defined new palette is defined in the SDRAM, the following ...
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STV3550 Figure 33. OSD CLUT programming flowchart Header Palettep[31:0] Memory Space 1st Color 2nd Color 4th Color 256th Color Palette with n Colors nth Color Memory Space 32 bits SDRAM In this example, the 4th color of the palette (programmed ...
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Graphics functional description Pixel mixing mode In pixel mixing mode, the only mixing factor applied is the Alpha mixing factor parameter (Alpha[7:0]) programmed in the CLUT. Global mixing mode In global mixing mode, the mixing factor applied is the mix-weight ...
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STV3550 There are different types of processes that must also be selected: ● Read/Write (with or without filtered Data compression) ● Parity checksum ● Simple transfer ● Color key based transfer: data transfered if different from a specified color (i.e. ...
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Graphics functional description 4.3 Graphics applications examples In addition to the menus required for the user interface, certain graphic applications are supported by the STV3550. 4.3.1 Teletext 1.5 ● 40-character width by 26-character (12 x 10) rows Note: Specific font ...
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STV3550 4.3.3 TeleWeb ● Full support of authored content in a 640 x 480 pixel area ● Minimum color resolution of 12 bit (RGB = 444), 24 bit recommended ● Support for a minimum of 196 colours (the default CLUT) ...
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Graphics functional description 4.4 Picture compositor The picture compositor is used to mix the video plane improved by the picture structure improvement (YSI/CTI) module in the video display pipeline, with the graphics plane from the OSD pipeline. The picture compositor ...
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STV3550 The picture compositor is a real-time multilayer (or multiplane) digital mixer. It can compose a single output stream from up to four sources: ● Background color plane (programmable register) ● Video plane (D1 input, once captured into the local ...
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Graphics functional description Table 16. List of accepted picture compositor formats Formats Description RGB888 24-bit RGB (RGB24) Bitmapped graphics with 8-bit per pixel (256 colors). For graphics, the CLUT output is 8-bit per color component (RGB) and 8 bit for ...
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STV3550 5 Output stage Note: Some descriptions in this section are not applicable for LCD applications. 5.1 Color space adaptor (CSA) and interpolator 5.1.1 Main features ● RGB to YUV convertion ● Up-sampling by two ● GFX_ACTIVE programmable delay 5.1.2 ...
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Output stage Figure 40. Color space adaptor block diagram RGB2YUV_EN 30 CLK_PIX Note: RGB to YUV conversion and color filter functions are not used in LCD applications 5.1.4 GFX_ACTIVE signal The chip delivers a GFX_ACTIVE signal that is high during ...
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STV3550 Table 17. Delay on rising/falling edges of GFX_ACTIVE signal (continued) DELAY_RISE Delay value 0011 CSA Stage Number - 4 clock cycles 0100 CSA Stage Number - 3 clock cycles 0101 CSA Stage Number - 2 clock cycles 0110 CSA ...
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Output stage 5.3 Perfect color engine (PCE) PCE dithers an input 10-bit video stream down to 4-6-8-10 output bits.The dithering is done in space and time in such a way that the eye does not perceive objectionable artifacts such as: ...
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STV3550 case i_hsync = hs_pix The HSYNC output pad is in the ‘clk_dac’ domain. We could delay the first edge (2 period) and we could adjust the pulse width (2 5.5.1 Csync output capability In the Csync mode the Hsync ...
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Output stage Table 18. Pinout (continued) STV3550 Basic STV3550 pin output 3x10 pad number bits 205 P3 R3 206 P4 R4 208 P10 G0 7 ...
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STV3550 Table 19. SWAP output STV3550 pin number 202 203 204 205 206 208 Table 20 ...
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Output stage Table 20. Multiplex output STV3550 pin STV3550 pad number 202 P0 203 P1 204 P2 205 P3 206 P4 208 P10 7 P11 8 P12 9 P13 10 ...
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STV3550 5.5.3 Data enable output This signal is fully generated according to the control register value. The user must assume the video window is correct according to the display data (video + OSD + background). Figure 44. Data enable output ...
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Output stage Figure 45. Data clock output clk_dac We could also select an output of the original clock frequency or the clock frequency divided by 2. 5.5.5 Pad control If a PAD is not used by the Video application a ...
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STV3550 5.5.6 Register We have a dedicated register interface (STbus T1). Table 21. STBus T1 Register Address 0x18 0x14 0x10 0x0C 0x08 0x04 0x00 Output stage Description Pad output Pad Control DE Vertical control DE Horizontal control Vsync control Hsync ...
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CPU and system management functional description 6 CPU and system management functional description 6.1 ST20 C2C200 CPU core This is the 32-bit ST20 C2C200 CPU core from the ST20 CPU family with a programmable operating frequency between 4 MHz and ...
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... The maximum ROM size is 16 MBits (or 2 MBytes), as the device is connected on 20 address lines and 16 data lines. Typical Flash devices, such as STM-29W160DT (STMicroelectronics) or AM29BL162C (AMD) are compliant with the STV3550 memory interface. The RAM device should be a Synchronous DRAM (SDRAM). A dedicated clock pad is available on the STV3550 ...
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CPU and system management functional description Note: For SDRAM, the address bus is multiplexed on 14 address lines (row, column and bank addresses), while Flash devices do not use multiplexed addresses. 6.3.4 Control registers The STV3550 memory interface is able ...
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STV3550 By sharing functions, the number of required pins is reduced, since the STV3550 is not able to access both Flash and SDRAM devices at the same time. Pins have been named according to their function when used in a ...
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CPU and system management functional description 6.3.8 STV3550 memory interface capabilities regarding Flash device Supported Flash commands The STV3550 is able to read the Flash memory like an asynchronous memory device. Write operations in Flash require specific sequences on the ...
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STV3550 Figure 46. Access cycle timings ADDR[19:0] t CSr1/ NOT_CS_FLASH NOT_CAS (NOT_OE) FLASH_D[15:0] (write) FLASH_D[15:0] (read) RD_NOT_WR Default settings for boot operation The STV3550 system clock frequency is 27 MHz when the boot sequence is executed. Below are the default ...
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CPU and system management functional description 6.3.9 STV3550 memory interface capabilities regarding SDRAM device Supported SDRAM commands The STV3550 memory interface supports the following SDRAM commands: ● Mode register set ● Row activate ● Precharge all ● Read and write ...
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STV3550 Table 23. SDRAM commands Commands Strobe state NOT_RAS NOT_CAS Precharge 0 1 all Row 0 1 Activate Write 1 0 Read 1 0 Mode 0 0 Register Set CBR 0 0 Refresh Operation 1. Address bit ...
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CPU and system management functional description Figure 48. Typical write access cycle CKOUT_SDRAM ADDR[16:15], ADDR[11:0] NOT_CS_SDRAM NOT_RAS NOT_CAS RD_NOT_WR NOT_BE[1:0] (ADDR[19:18]) SDRAM_D[15:0] (FLASH_D[15:0]) Figure 49. Typical read access cycle (CAS latency=2) CKOUT_SDRAM ADDR[16:15], ADDR[11:0] NOT_CS_SDRAM NOT_RAS NOT_CAS RD_NOT_WR NOT_BE[1:0] (ADDR[19:18]) ...
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STV3550 Figure 50. Typical refresh access cycle CKOUT_SDRAM NOT_CAS NOT_RAS NOT_CS_SDRAM RD_NOT_WR 6.3.10 SDRAM low power mode The STV3550 is able to set the SDRAM into low power mode. Most SDRAM devices have a clock enable input pin that internally ...
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CPU and system management functional description Figure 51. Low-cost configuration NOT_CS_FLASH ADDR[19:0] FLASH_D[15:0] NOT_CS_SDRAM NOT_RAS NOT_CAS RD_NOT_WR NOT_BE[1:0] STV3550 SDRAM_D[15:0] CKOUT_SDRAM CKIN_SDRAM High-end configuration with one SDRAM device This configuration requires a SDRAM with 32 data lines. A typical size ...
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STV3550 Figure 52. High-end configuration using 1 SDRAM device NOT_CS_FLASH ADDR[19:0] FLASH_D[15:0] NOT_CS_SDRAM NOT_RAS NOT_CAS RD_NOT_WR NOT_BE[1:0] STV3550 SDRAM_D[15:0] CKOUT_SDRAM CKIN_SDRAM High-end configuration with two SDRAM devices This configuration requires two SDRAM devices with 16 data lines each. A typical ...
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CPU and system management functional description Figure 53. High-end configuration using 2 SDRAM devices NOT_CS_FLASH ADDR[19:0] FLASH_D[15:0] NOT_CS_SDRAM NOT_RAS NOT_CAS RD_NOT_WR NOT_BE[1:0] STV3550 SDRAM_D[15:0] CKOUT_SDRAM CKIN_SDRAM Mixed configuration with two SDRAM devices This configuration is able to implement low-cost and ...
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STV3550 When the board is dedicated to high-end solutions, both SDRAMs are soldered and the STV3550 memory interface is configured by software to use both SDRAMs. Byte enable signals are provided as described in previous sections, depending on the memory ...
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CPU and system management functional description 6.3.12 STV3550 external and internal memory mapping The internal and external memory maps in the STV3550 is described in Figure 55. Internal and external memory map STV3550 Address Space 7FFFFFFF 7FFFFFFF 7FFE0000 67FFFFFF 50000000 ...
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STV3550 6.4.1 External hard reset Figure 56. External hard reset NRESET Reset Pad An external hard reset is triggered by asserting a low state on the NRESET pin of the STV3550. Assertion and de-assertion are considered as asynchronous events. On ...
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CPU and system management functional description Flash market, so the ST20 C2C200 CPU core is able to execute the first application tasks, which are: ● To speed-up the system clock from 27 MHz to the standard operating frequency by configuring ...
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STV3550 In standby mode, only the following blocks are clocked: ● Infrared preprocessor ● RTC ● ADC In addition to standby mode, the STV3550 includes various low power modes. These modes are performed by reducing the clock frequency for each ...
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CPU and system management functional description Table 24. Interrupt sources Number of Interrupt source name interrupts OSD 4 Video Display Pipeline 5 SDIN 19 VTG 5 Peripherals and I/Os 20 2DBM 2 Line-locked PLL 1 TOTAL 56 6.8 Clock generator ...
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STV3550 Figure 58. Clock frequency domains Build-Up NRESET Counter 27 MHz HV Filter 8 YCRCB[7:0] TNR CLK_DATA HSYNC SDIN VSYNC Block 27 MHz EXTALIN Clock 27 MHz Generator CPU and system management functional description Video Picture Pipeline Compositor CSA YSI/CTI ...
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TV chassis control 7 TV chassis control The STV3550 includes the following peripherals for TV chassis control: ● 30 fully-programmable I/Os ● Four external interrupts ● 8-bit programmable PWM with 4 inputs/outputs ● Infrared digital preprocessor ● Real time clock ...
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STV3550 When the PWM counter starts, the output is set to 1. When the counter matches the PWM compare value, the output is reset to 0. The output will return to 1 when the counter overflows. 7.1.3 Counter functions This ...
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TV chassis control If a new edge is detected and if both registers (IRP0 and IRP1) are not empty, the new edge cannot be taken into account until both registers are reset (the interval is not measured). An internal algorithm ...
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STV3550 Figure 60. WDT behaviour Watchdog Counter Value notRST Watchdog Reset Generated Note: The counter is described as a counter that counts from zero up to the maximum allowed number. 7.3.1 Clearing the counter The watchdog counter is cleared under ...
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TV chassis control Both counters increment at 1.024 kHz. Because the RTC must run continuously, the counters are not reset by the software or Watchdog reset. Only a global external chip reset will reset the counters. 7.4.1 RTC counters Because ...
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STV3550 Figure 61. Basic timer block diagram Timer Input Clock Control Logic Timer Output 7.5.1 Functional description Timer/counter control The timer can run in continuous or single mode. An initial pre-scale or counter value can be loaded. Note: In order ...
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TV chassis control high, the basic timer count operation proceeds. When the status of the input timer pin is low, the counting is stopped ● Triggerable input mode: The basic timer is triggered only once by: – enabling the timer ...
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STV3550 Figure 62. ADC diagram AD[0] AD[1] AD[2] AD[3] AD[4] AD[5] Ext. Trigger 7.6.1 Main features ● 10-bit resolution with a guaranteed accuracy of 6 bits ● six selectable analog inputs ● Single conversion time: 4.75 µs @ ...
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TV chassis control End of conversion interrupt An interrupt can be generated at the end of each conversion. Analog watchdog interrupt Moreover, another interrupt can be generated based on the upper or lower threshold limits of the watchdog. 1-channel mode ...
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STV3550 Power off mode At reset, the ADC is in power off mode. In power off mode, the ADC consumes zero power. To switch into power on mode, you must first pass through standby mode and wait for a stabilization ...
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TV chassis control The SSC2 itself has clock in/out and data in/out pins for connection to the two pads and a pin control block which selects the relevant data input and output according to the master or slave mode set. ...
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STV3550 7.7.3 PIO pad connection and control In I²C mode, only the SDA pad will be used as an input and output. The SDA and SCL pads are provided by 2 bits of a standard ST20 PIO block. Their directions ...
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TV chassis control 7.7.5 Clock control In master mode, the serial clock, SCL, is generated by the SSC2 according to the setting of the phase, SSCPH, and polarity, SSCPO bits in the control register. The polarity bit, SSCPO, defines the ...
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STV3550 Baudrate Where SSCBRG represents the content of the reload register unsigned 16-bit integer and f represents the CPU clock frequency. CPU At a CPU clock frequency of 40 MHz, the following baud rates are generated as shown ...
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TV chassis control placed into the LSB of the register and taken out of the MSB of the programmed data width. This is shown for a 9-bit data frame in Figure 68. Shift register operation for 9-bit data frames MSB ...
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STV3550 Figure 69. Clock edge detection (rising edge) System Clock Serial_Clock_In Sampling Points 7.7.8 Receive data sampling The data received by the SSC2 is sampled after the latching edge of the input clock. The latching edge being determined by the ...
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TV chassis control 7.7.9 Transmit and receive buffers The transmit and receive buffers are used to allow the SSC2 to do back-to-back transfers (i.e. continuous clock and data transmission). The transmit buffer (SSCTBUF), is written with the data to be ...
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STV3550 7.7.12 Master/slave operation A number of features of the SSC2 are controlled by whether the block is in master or slave mode. For example, in master mode the SSC2 will generate the serial_clock signal according to the setting of ...
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TV chassis control Phase error A phase error can be generated in master and slave modes. It indicates that the data received at the incoming data pin has changed during the time from one sample before the latching clock edge ...
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STV3550 The reset is performed by setting the SSCSR bit in the SSCCON register. While the bit is set the entire SSC2 functionality will be held in the reset state. That is ALL functionality, except for the current settings of ...
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TV chassis control I²C control There are a number of features of the I²C-bus protocol which require special control allow slow slave devices to be accessed, and to allow multiple master devices to generate a consistent clock signal, ...
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STV3550 In order to program for I²C mode, a separate control register is provided, SSCI2C. To perform any of the I²C hardware features, the I²C control enable bit, SSCI2CM, must be set. When the I²C control bit is set, the ...
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TV chassis control Until the status bit is reset, the SSC2 will hold the clock line LOW at the end of the current data frame. This forces the winning master device to wait until the software has processed the interrupt. ...
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STV3550 Figure 73. Clock synchronisation mechanism Master 1 Master 2 Resultant Clock Slave Stretched The SSC2 implements this clock synchronization mechanism when the I²C control bit, SSCI2CM, is enabled. 7.7.19 START/STOP condition detection START/STOP conditions are only generated by a ...
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TV chassis control 7.7.20 Slave address comparison After a START condition has been detected, the SSC2 goes into the address comparison phase. It receives the first 8 bits of the next byte transmitted and compares the first 7 bits against ...
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STV3550 occur after the second byte plus acknowledge). This gives the software interrupt routine time to initialize for transmission or reception of data. 2. When the SSC2 is in slave mode and is transmitting or receiving. The clock stretch occurs ...
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TV chassis control 7.7.23 Acknowledge bit generation For I²C operation required to both detect acknowledge bits when transmitting data, and generate them when receiving data. An acknowledge bit must be transmitted by the receiver at the end of ...
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STV3550 7.7.25 I²C timing specification The I²C specification defines a number of timing constraints which must be met on the output clock and data pins. The key values which must be met are described in Table 27. Key I SCL ...
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TV chassis control 2 Table 28 timing constants (continued) I²C timing name Hold Time (repeated) START Condition T HD:STA Data Setup Time T 7.8 Asynchronous serial controller (ASC) The ASC, also referred to as the UART interface, provides ...
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STV3550 A transmission is started by writing to the transmit buffer register ASC_n_TxBuffer. Because data transmission is double-buffered or uses a FIFO (selectable in the ASC_n_Control register), a new character may be written to the transmit buffer register before the ...
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TV chassis control Figure 74. 8-bit T x data frame format start bit 9-bit data frames Figure 75 illustrates a 9-bit transmitted data frame. 9-bit data frames use of one of the following formats: ● Nine data bits D0-8 (Mode ...
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STV3550 7.8.3 Transmission Transmission begins at the next baud rate clock tick, provided that the run bit is set and data has been loaded into the ASC_n_TxBuffer. If the CTSEnable bit is set in the ASC_n_Control register then transmission only ...
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TV chassis control 7.8.4 Reception Reception is initiated by a falling edge on the data input pin RxD, provided that the Run and RxEnable bits of the ASC_n_Control register are set. Controlled data transfer can be achieved using the RTS ...
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STV3550 If the mode is one where a parity bit is expected, then the next bit (bit 8 of 0-9) records whether there was a parity error when that entry was received. It does not contain the parity bit that ...
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TV chassis control The TimeoutNotEmpty bit of the ASC_n_Status register is ‘1’ when the input FIFO is not empty and the time-out counter is zero. The TimeoutIdle bit of the ASC_n_Status register is ‘1’ when the input FIFO is empty ...
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STV3550 Writes to the ASC_n_BaudRate register update the reload register value. Reads from the ASC_n_BaudRate register return the current value of the counter. Mode 1 When the BaudMode bit in the ASC_n_Control register is set to 1, the baud rate ...
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TV chassis control The status bits cannot be reset by software because the ASC_n_Status register cannot be written to directly. Status bits are reset by operations performed by the interrupt handler: ● Transmitter interrupt status bits (TxEmpty, TxHalfEmpty) are reset ...
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STV3550 As shown in Figure indicates the completed transmission of the data field of the frame. Therefore, software using handshake should rely on TxEmpty at the end of a data block to make sure that all data has really been ...
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TV chassis control Figure 79. ASC reception Receive Input Shift Register ASCRxBuffer Register RxBufFull 7.9 IrDA encoder/decoder The IrDA encoder/decoder performs the modulation/demodulation used to both encode and decode the electrical pulses sent between the IR Transceiver and the UART. ...
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STV3550 7.9.1 Encoding scheme The encoder sends a pulse for every space or ‘0’ that is sent on the I_UARTF_TXD line high to low transition of the I_UARTF_TXD line, the generation of the pulse is delayed for 7 ...
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TV chassis control 7.9.3 Register There is not a dedicated register interface (STBus T1), only a single ‘I_IRDA_ON’ primary input with a reset value of ‘0’. When the IrDA block is ‘off’ (bit equal to ‘0’), the block is bypassed. ...
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STV3550 8 Package mechanical data Figure 83. 208-pin plastic quad flat package D1 D3 156 157 208 1 e Exact shape of each corner is optional. Table 29. JEDEC standard package dimensions mm Dim Minimum Typical A A1 0.25 A2 ...
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Package mechanical data Table 29. JEDEC standard package dimensions (continued) mm Dim Minimum Typical E1 28.00 E3 25.50 L 0.45 0.60 L1 1.30 K 0° 3.5° 8.1 Environmentally-friendly packages In order to meet environmental requirements, ST offers these devices in ...
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STV3550 9 Electrical characteristics The STV3550 contains circuitry used to protect inputs against damage due to high static voltage or electric fields. Nevertheless recommended that normal precautions be observed in order to avoid subjecting this high-impedance circuit to ...
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Electrical characteristics 9.2 Thermal data Table 31. Thermal data Symbol T Ambient temperature range AMB T Storage temperature range STG T Junction temperature J Maximum thermal resistance (junction-to- R thJA ambient) 9.3 DC electrical characteristics ( 70°C; ...
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STV3550 Table 32. DC electrical characteristics (continued) Symbol Parameter HSYNC/VSYNC input low V ILVH level HSYNC/VSYNC input V HYHV hysteresis I Reset pin input LKRS A/D pin input leakage I LKAD current XTALIN pin input leakage I LKOS current 1. ...
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Electrical characteristics 9.5 H/V synchronization characteristics Table 34. H/V synchronization characteristics Symbol Parameter Output luma/sync non- alignment Output chroma/sync non- alignment Line-PLL capture range Time constant to recover 40 µs of phase shift HSYNC uncertainty in relation to RGB/YCrCb outputs ...
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STV3550 9.7 ADC characteristics (VCC33_ADC = 3.3 V ±10%; CLK_ADC (Typ.) = 3.4 MHz; T otherwise specified). Table 36. Analog parameters Symbol Parameter Analog input range Conversion time fast/slow Power-up time Resolution Differential non linearity Integral non linearity Absolute accuracy ...
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Electrical characteristics 2 9 bus characteristics 2 Table 37. Key I C timing requirements Parameter SCL clock frequency Hold time of SCL after SDA START or REPSTART condition. After this time the first clock low pulse is created ...
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STV3550 Figure 85. I2C bus timing SDA t BUF SCL SDA t LOW t HD,STA HD,DAT t SU,STA Electrical characteristics t SU,DAT t HIGH SU,STO 139/145 ...
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Timing specifications 10 Timing specifications The timings are based on the following conditions unless otherwise stated: 1. Input rise and fall times (between 10% and 90%). 2. Output load = Output threshold = 1.5 ...
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STV3550 10.2 Reset timings The t value specified in the following table and figure is for power-on reset when RSTHRSTL the device is cold. Warm reset parameters (when the clock and power supply are stable) will fall within these limits ...
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Timing specifications 10.4 TAP timings Table 41. TAP timings Symbol t TCK period TCHTCH t TAP inputs valid to TCK high TIVTCH t TAP input hold after TCK high TCHTIX t TCK low to TAP output valid TCHTOV Figure 89. ...
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STV3550 Figure 90. SDIN input video stream input timings Equivalent to 120 MBit/s input rate 10.6 Output video port interface (AC electrical characteristics) Table 43. Normal mode (single edge clock output) Symbol Output operating frequency for: f DCLK D CLK ...
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Revision history 11 Revision history Table 45. Document revision history Date June 2003 October 2003 January 2004 February 2004 20-Feb-2009 144/145 Revision 1.0 First draft 1.1 Correction to XTALOUT and XTALIN pin number assignments 1.2 Various corrections, modifications and updates ...
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... STV3550 Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. ...