STV3550B STMicroelectronics, STV3550B Datasheet - Page 111

• Manufacturer Part Number: STV3550B
• Manufacturer: STMicroelectronics

Specifications of STV3550B

• Operating Temperature (min): 0C
• Operating Temperature (max): 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / Rohs Status: Compliant

STV3550
TV chassis control
In order to program for I²C mode, a separate control register is provided, SSCI2C.
To perform any of the I²C hardware features, the I²C control enable bit, SSCI2CM, must be
set.
When the I²C control bit is set, the clock synchronization mechanism is always enabled.
When the I²C control bit is set the START and STOP condition detection is performed.
To program the slave address of the SSC2 the slave address register, SSCSLAD must be
written to with the address value. In the case of 7 bit addresses, only 7 bits should be
written. For 10-bit addressing, the full 10 bits are written to. The SSC2 then uses this
register to compare the slave address transmitted after a START condition.
To perform 10-bit address comparison and address acknowledge generation, the 10-bit
addressing mode bit, SSCAD10 must be set.
The clock stretching mechanism is enabled for various interrupt conditions when the I²C
control enable bit, SSCI2CM is set.
To generate a START condition, the I²C START condition generate bit, SSCSTRTG, must be
set.
To generate a STOP condition, the I²C STOP condition generate bit, SSCSTOPG, must be
set.
To generate acknowledge bits (i.e. a LOW data bit), after each 8 bit data byte when receiving
data, the acknowledge generation bit, SSCACKG, must be set. When receiving data as a
master, this bit must be reset to 0 before the final data byte is received, thereby signalling to
the slave to stop transmitting.
To indicate to the software that various situations have arisen on the I²C-bus, a number of
status bits are provided in the status register, SSCSTAT. In addition, some of these bits can
generate interrupts if corresponding bits are set in the interrupt enable register, SSCIEN.
To indicate that the SSC2 has been accessed as a slave device, the addressed as slave bit,
SSCAAS, is set. This will also cause an interrupt if the SSCAASEN bit is set in the interrupt
enable register.
The interrupt will occur after the SSC2 has generated the address acknowledge bit. In 10 bit
addressing mode, the interrupt will occur after the second byte acknowledge bit, in the
situations where 2 bytes of address are sent, or it will occur after the first byte acknowledge
in the situation where only one byte is required.
Until the status bit is reset, the SSC2 will hold the clock line LOW. This forces the master
device to wait until the software has processed the interrupt.
The status bit and the interrupt are reset by writing to the transmit buffer, SSCTBUF.
To indicate that a STOP condition has been received the STOP condition detected bit,
SSCSTOP is set. This will also cause an interrupt if the SSCSTOPEN bit is set in the
interrupt enable register.
The SSCSTOP interrupt and status bit will be reset by a read of the status register,
SSCSTAT.
To indicate that the SSC2 has lost the arbitration process, when in a multi-master
configuration, the arbitration lost bit, SSCARBL, is set. This will also result in an interrupt if
the SSCARBLEN bit is set in the interrupt enable register. The interrupt will occur
immediately after the arbitration is lost.
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