MAX5556ESA+T Maxim Integrated Products, MAX5556ESA+T Datasheet - Page 9

• Manufacturer Part Number: MAX5556ESA+T
• Description: IC DAC STEREO AUDIO 8-SOIC
• Manufacturer: Maxim Integrated Products

Specifications of MAX5556ESA+T

• Number Of Bits: 16
• Data Interface: Serial
• Number Of Converters: 2
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power Dissipation (max): -
• Settling Time: -

The MAX5556 strobes serial data (SDATA) in on the ris-
ing edge of SCLK. LRCLK routes data to the left or right
outputs and, along with SCLK, defines the number of
bits per sample transferred. The digital interpolators fil-
ter data at internal clock rates derived from the MCLK
frequency. Each device supports both internal and
external serial clock (SCLK) modes.
The serial interface strobes data (SDATA) in on the ris-
ing edge of SCLK, MSB first. The MAX5556 supports
four different data formats, as detailed in Figure 4.
Figure 4. MAX5556 Data Format Timing
Figure 5. External SCLK Serial Timing Diagram
LRCLK
SDATA
SCLK
MSB
-1
_______________________________________________________________________________________
-2
-3
Clock and Data Interface
LRCLK
SDATA
-4 -5
SCLK
• I
• I
32 x f
SCLK = 48 X f
2
2
S, 16-BIT DATA AND INTERNAL SCLK =
S, UP TO 24 BITS OF DATA AND INTERNAL
INTERNAL SERIAL CLOCK MODE
S
IF MCLK/ LRCLK = 256 OR 512
+5
+4
S
IF MCLK/ LRCLK = 384
+3
DATA DIRECTED TO OUTL
+2
t
SLRH
SDATA Input
+1
LSB
Low-Cost Stereo Audio DAC
t
SDS
• I
• DATA VALID ON RISING EDGE OF SCLK
2
S, UP TO 24 BITS OF DATA
EXTERNAL SERIAL CLOCK MODE
SCLK strobes the individual data bits at SDATA into the
DAC. The MAX5556 operates in one of two modes:
internal serial clock mode or external serial clock mode.
The MAX5556 operates in external serial clock mode
when SCLK activity is detected. The device returns to
internal serial clock mode if no SCLK signal is detected
for one LRCLK period. Figure 5 details the external serial
clock mode timing parameters.
t
SLRS
MSB
-1
t
SDH
-2
t
SCLKL
-3 -4
t
SCLK
t
SCLKH
+5
+4
+3
DATA DIRECTED TO OUTR
+2
+1
LSB
External SCLK Mode
Serial Clock (SCLK)
9