SPC5123YVY400B Freescale Semiconductor, SPC5123YVY400B Datasheet - Page 45

• Manufacturer Part Number: SPC5123YVY400B
• Manufacturer: Freescale Semiconductor

Specifications of SPC5123YVY400B

• Lead Free Status / Rohs Status: Compliant

Faster ATA modes (i.e., UDMA 0, 1, 2) are supported when the system is running at a sufficient frequency to provide adequate
data transfer rates. Adequate data transfer rates are a function of the following:
The ATA clock is the same frequency as the IP bus clock in MPC5121e/MPC5123. See the MPC5121e/MPC5123 Reference
Manual.
3.3.9.1
In the timing equations, some timing parameters are used. These parameters depend on the implementation of the ATA interface
in silicon, the bus transceiver used, the cable delay and cable skew. The parameters shown in
Freescale Semiconductor
tcable1
tcable2
tskew1
tskew2
tskew3
Name
ti_dh
ti_ds
•
•
•
tbuf
tsui
tco
tsu
thi
T
The MPC5121e/MPC5123 operating frequency (IP bus clock frequency)
Internal MPC5121e/MPC5123 bus latencies
Other system load dependent variables
PATA Bus clock period
Set-up time ATA_DATA to ATA_IORDY edge (UDMA-in only)
Hold time ATA_IORDY edge to ATA_DATA (UDMA-in only)
Propagation delay bus clock L-to-H to: ATA_CS0, ATA_CS1, ATA_DA2,
ATA_DA1, ATA_DA0, ATA_DIOR, ATA_DIOW, ATA_DMACK, ATA_DATA,
ATA_BUFFER_EN
Set-up time ATA_DATA to bus clock L-to-H
Set-up time ATA_IORDY to bus clock H-to-L
Hold time ATA_IORDY to bus clock H to L
Max difference in propagation delay bus clock L-to-H to any of following
signals: ATA_CS0, ATA_CS1, ATA_DA2, ATA_DA1, ATA_DA0, ATA_DIOR,
ATA_DIOW, ATA_DMACK, ATA_DATA (WRITE), ATA_BUFFER_EN
Max difference in buffer propagation delay for any of following signals:
ATA_CS0, ATA_CS1, ATA_DA2, ATA_DA1, ATA_DA0, ATA_DIOR,
ATA_DIOW, ATA_DMACK, ATA_DATA (WRITE), ATA_BUFFER_EN
Max difference in buffer propagation delay for any of following signals:
ATA_IORDY, ATA_DATA (read)
Max buffer propagation delay
Cable propagation delay for ata_data
Cable propagation delay for control signals: ATA_DIOR, ATA_DIOW,
ATA_IORDY, ATA_DMACK
PATA Timing Parameters
All output timing numbers are specified for nominal 50 pF loads.
Table 3-25. PATA Timing Parameters
MPC5121E/MPC5123 Data Sheet, Rev. 3
Meaning
NOTE
Electrical and Thermal Characteristics
Controlled by
MPC5121E/M
MPC5121E/M
MPC5121E/M
MPC5121E/M
MPC5121E/M
MPC5121E/M
MPC5121E/M
MPC5121E/M
Transceiver
Transceiver
Transceiver
Table 3-25
PC5123
PC5123
PC5123
PC5123
PC5123
PC5123
PC5123
PC5123
Cable
Cable
specify the ATA timing.
Value
1.7 ns
15 ns
2 ns
5 ns
2 ns
2 ns
2 ns
2 ns
SpecID
A9.10
A9.11
A9.12
A9.13
A9.1
A9.2
A9.3
A9.4
A9.5
A9.6
A9.7
A9.8
A9.9
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